參數(shù)資料
型號(hào): GS8330DW36C-250
廠商: Electronic Theatre Controls, Inc.
英文描述: RECTIFIER FAST-RECOVERY SINGLE 1A 50V 30A-ifsm 1.2V-vf 200ns 5uA-ir DO-41 5K/AMMO
中文描述: 雙晚寫(xiě)SigmaRAM
文件頁(yè)數(shù): 6/30頁(yè)
文件大?。?/td> 583K
代理商: GS8330DW36C-250
Rev: 1.00 6/2003
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
6/30
2003, GSI Technology, Inc.
Preliminary
GS8330DW36/72C-250/200
Double Late Write
Double Late Write means that Data In is required on the third rising edge of clock. Double Late Write is used to implement Pipeline
mode NBT SRAMs.
Byte Write Control
The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,
including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle.
Example of x36 Byte Write Truth Table
Function
W
Ba
Bb
Bc
Bd
Read
H
X
X
X
X
Write Byte A
L
L
H
H
H
Write Byte B
L
H
L
H
H
Write Byte C
L
H
H
L
H
Write Byte D
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort
L
H
H
H
H
SigmaRAM Double Late Write with Pipelined Read
ADV
DD
Read
Write
Read
Write
Read
C
D
F
E
CK
Address
A
B
/E
1
/W
DQ
QA
CQ
Key
QC
Hi-Z
Access
DB
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