參數(shù)資料
型號(hào)： GS8330DW36C-250
廠商： Electronic Theatre Controls, Inc.
英文描述： RECTIFIER FAST-RECOVERY SINGLE 1A 50V 30A-ifsm 1.2V-vf 200ns 5uA-ir DO-41 5K/AMMO
中文描述： 雙晚寫SigmaRAM
文件頁(yè)數(shù)： 13/30頁(yè)
文件大?。?/td> 583K
代理商： GS8330DW36C-250
Rev: 1.00 6/2003
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
13/30
2003, GSI Technology, Inc.
Preliminary
GS8330DW36/72C-250/200
Double Late Write, Pipelined Read Truth Table
CK
E1
(t
n
)
E
(t
n
)
ADV
(t
n
)
W
(t
n
)
B
(t
n
)
Previous
Operation
Current Operation
DQ/CQ
(t
n
)
DQ/CQ
(t
n+1
)
DQ/CQ
(t
n+2
)
0
→
1
X
F
0
X
X
X
Bank Deselect
***/***
Hi-Z/Hi-Z
---
0
→
1
X
X
1
X
X
Bank Deselect
Bank Deselect (Continue)
Hi-Z/Hi-Z
Hi-Z/Hi-Z
---
0
→
1
1
T
0
X
X
X
Deselect
***/***
Hi-Z/CQ
---
0
→
1
X
X
1
X
X
Deselect
Deselect (Continue)
Hi-Z/CQ
Hi-Z/CQ
---
0
→
1
0
T
0
0
T
X
Write
Loads new address
Stores DQx if Bx = 0
***/***
***/***
D1/CQ
0
→
1
0
T
0
0
F
X
Write (Abort)
Loads new address
No data stored
***/***
***/***
Hi-Z/CQ
0
→
1
X
X
1
X
T
Write
Write Continue
Increments address by 1
Stores DQx if Bx = 0
***/***
Dn-1/CQ
Dn/CQ
0
→
1
X
X
1
X
F
Write
Write Continue (Abort)
Increments address by 1
No data stored
***/***
Dn-1/CQ
Hi-Z/CQ
0
→
1
0
T
0
1
X
X
Read
Loads new address
***/***
Q1/CQ
---
0
→
1
X
X
1
X
X
Read
Read Continue
Increments address by 1
Qn-1/CQ
Qn/CQ
---
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
If E2 = EP2 and E3 = EP3, then E = “T” else E = “F”.
If one or more Bx = 0, then B = “T” else B = “F”.
“1” = input “high”; “0” = input “l(fā)ow”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
“***” indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.
“---” indicates that the DQ input requirement / output state and CQ output state are determined by the next operation.
DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.
Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces
of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial exter-
nal (base) address.
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