參數(shù)資料
型號(hào): GS832418C-250
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
中文描述: 2M X 18 CACHE SRAM, 6 ns, PBGA209
封裝: 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁(yè)數(shù): 18/46頁(yè)
文件大?。?/td> 1149K
代理商: GS832418C-250
Rev: 1.00 10/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
18/46
2001, Giga Semiconductor, Inc.
Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
Simplified State Diagram with G
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Notes:
1.
2.
The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
3.
相關(guān)PDF資料
PDF描述
GS832418C-250I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832436B-133 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832436B-133I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832436B-150 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS832436B-150I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
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