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參數(shù)資料
| 型號： | GS820E32A |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 2Mb（64K x 32Bit) Synchronous Burst SRAM(2M位（64K x 32位）同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）) |
| 中文描述： | 2MB的（64K的x 32位）同步突發(fā)靜態(tài)存儲器（200萬位（64K的× 32位）同步靜態(tài)隨機(jī)存儲器（帶2位脈沖地址計(jì)數(shù)器）） |
| 文件頁數(shù)： | 7/23頁 |
| 文件大?。?/td> | 344K |
| 代理商： | GS820E32A |
Rev: 1.04 3/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
7/23
2000, Giga Semconductor, Inc.
E
GS820E32AT/Q-150/138/133/117/100/66
Simplified State Diagram
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
S
S
CR
R
CW
CR
CR
Notes:
1.
2.
The diagramshows only supported (tested) synchronous state transitions. The diagrampresumes G is tied Low.
The upper portion of the diagramassumes active use of only the Enable (E
1,
E
2,
E
3
) and Write (B
A
B
, B
C
, B
D
, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.
The upper and lower portions of the diagramtogether assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
3.
相關(guān)PDF資料 |
PDF描述 |
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| GS820E32T-6I | 2M Synchronous Burst SRAM |
| GS820E32Q-100 | 2M Synchronous Burst SRAM |
| GS820E32Q-117 | 2M Synchronous Burst SRAM |
| GS820E32Q-133 | 2M Synchronous Burst SRAM |
| GS820E32Q-133I | 2M Synchronous Burst SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS820E32AGT-133 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:64K x 32 2Mb Synchronous Burst SRAM |
| GS820E32AGT-133I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:64K x 32 2Mb Synchronous Burst SRAM |
| GS820E32AGT-166 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:64K x 32 2Mb Synchronous Burst SRAM |
| GS820E32AGT-166I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:64K x 32 2Mb Synchronous Burst SRAM |
| GS820E32AGT-180 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:64K x 32 2Mb Synchronous Burst SRAM |
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