參數(shù)資料
型號: GS8161V36CGD-333I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
中文描述: 512K X 36 CACHE SRAM, 4.5 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, LEAD FREE, FBGA-165
文件頁數(shù): 6/28頁
文件大?。?/td> 584K
代理商: GS8161V36CGD-333I
GS8161V18/36CD-333/300/250
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 2/2005
6/28
2004, GSI Technology
Mode Pin Functions
Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Output Register Control
FT
H or NC
L or NC
Power Down Control
ZZ
H
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
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