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參數(shù)資料
| 型號： | GS816118D |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| 中文描述： | 1M×18，512k×32，512k×36 18M位同步突發(fā)靜態(tài)存儲器 |
| 文件頁數(shù)： | 26/36頁 |
| 文件大?。?/td> | 945K |
| 代理商： | GS816118D |
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GS816118(T/D)/GS816132(D)/GS816136(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.13 11/2004
26/36
1999, GSI Technology
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
Select DR
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
1
Select IR
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
Test Logic Reset
Run Test Idle
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
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PDF描述 |
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| GS816236BGD-250 | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816236BGD-250I | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS816118D-133 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:165 Bump BGA?x18 Commom I/O?Top View (Package D) |
| GS816118D-133I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:165 Bump BGA?x18 Commom I/O?Top View (Package D) |
| GS816118D-150 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:165 Bump BGA?x18 Commom I/O?Top View (Package D) |
| GS816118D-150I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:165 Bump BGA?x18 Commom I/O?Top View (Package D) |
| GS816118D-166 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:165 Bump BGA?x18 Commom I/O?Top View (Package D) |
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