參數(shù)資料
型號: GS816118D
廠商: Electronic Theatre Controls, Inc.
元件分類: DRAM
英文描述: 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
中文描述: 1M×18,512k×32,512k×36 18M位同步突發(fā)靜態(tài)存儲器
文件頁數(shù): 12/36頁
文件大?。?/td> 945K
代理商: GS816118D
GS816118(T/D)/GS816132(D)/GS816136(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.13 11/2004
12/36
1999, GSI Technology
Synchronous Truth Table
Operation
Address Used
State
Diagram
Key
5
X
R
R
W
CR
CR
CW
CW
E
1
ADSP
ADSC
ADV
W
3
DQ
4
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
1.
X = Don’t Care, H = High, L = Low
2.
W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
3.
G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
4.
All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
5.
Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See
BOLD
items above.
6.
Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See
ITALIC
items above.
None
External
External
External
Next
Next
Next
Next
Current
Current
Current
Current
H
L
L
L
X
H
X
H
X
H
X
H
X
L
H
H
H
X
H
X
H
X
H
X
L
X
L
L
H
H
H
H
H
H
H
H
X
X
X
X
L
L
L
L
H
H
H
H
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
Q
Q
D
Q
Q
D
D
Q
Q
D
D
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