參數(shù)資料
型號(hào): GS81032A
廠商: GSI TECHNOLOGY
英文描述: 1Mb(32K x 32Bit)Synchronous Burst SRAM(1M位(32K x 32位)同步靜態(tài)RAM(帶2位脈沖地址計(jì)數(shù)器))
中文描述: 1兆(32KX8的32位)同步突發(fā)靜態(tài)存儲(chǔ)器(100萬(wàn)位(32K的× 32位)同步靜態(tài)隨機(jī)存儲(chǔ)器(帶2位脈沖地址計(jì)數(shù)器))
文件頁(yè)數(shù): 3/23頁(yè)
文件大?。?/td> 756K
代理商: GS81032A
Rev: 1.00 12/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
3/23
2000, Giga Semiconductor, Inc.
GS81032AT/Q-150/138/133/117/100/66
TQFP Pin Description
Pin Location
Symbol
A
0
, A
1
Type
I
Description
37, 36
Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29
16, 38, 39, 42, 43, 66, 50, 51,
80, 1, 30, 49
87
93, 94
95, 96
89
88
98, 92
97
86
83
84, 85
64
14
31
A
2
–A
14
I
Address Inputs
DQ
A1
–DQ
A8
DQ
B1
–DQ
B8
DQ
C1
–DQ
C8
DQ
D1
–DQ
D8
I/O
Data Input and Output pins
NC
No Connect
BW
B
A
, B
B
B
C
, B
D
CK
GW
E
1
, E
3
E
G
ADV
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
ADSP, ADSC
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
15, 41, 65, 91
I
Core power supply
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
I
I/O and core ground
4, 11, 20, 27, 54, 61, 70, 77
I
Output driver power supply
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