- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄384345 > GS1561-CF (Gennum Corporation) GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer PDF資料下載
參數(shù)資料
| 型號(hào)： | GS1561-CF |
| 廠(chǎng)商： | Gennum Corporation |
| 英文描述： | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| 中文描述： | GS1560A/GS1561的HD - LINX進(jìn)程- R的第二雙率解串器 |
| 文件頁(yè)數(shù)： | 60/80頁(yè) |
| 文件大?。?/td> | 842K |
| 代理商： | GS1561-CF |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)當(dāng)前第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)
GS1560A/GS1561 Data Sheet
27360 - 8
September 2005
60 of 80
3.10.5.3 Lock Error Detection
The LOCKED pin of the GS1560A/GS1561 indicates the lock status of the
reclocker and lock detect blocks of the device. Only when the LOCKED pin is
asserted HIGH has the device correctly locked to the received data stream, (see
Lock Detect on page 35
).
The GS1560A/GS1561 will also indicate lock error to the host interface when
LOCKED = LOW by setting the LOCK_ERR bit in the ERROR_STATUS register
HIGH.
3.10.5.4 Ancillary Data Checksum Error Detection
The GS1560A/GS1561 will calculate checksums for all received ancillary data and
compare the calculated values to the received checksum words. If a mismatch is
detected, the error is flagged in the CCS_ERR and/or YCS_ERR bits of the
ERROR_STATUS register.
When operating in HD mode, (SD/HD = LOW), the device will make comparisons
on both the Y and C channels separately. If an error condition in the Y channel is
detected, the YCS_ERR bit will be set HIGH. If an error condition in the C channel
is detected, the CCS_ERR bit will be set HIGH.
When operating in SD mode, (SD/HD = HIGH), only the YCS_ERR bit will be set
HIGH when checksum errors are detected.
Although the GS1560A/GS1561 will calculate and compare checksum values for
all ancillary data types by default, the host interface may program the device to
check only certain types of ancillary data checksums.
This is accomplished via the ANC_TYPE register as described in
Programmable
Ancillary Data Detection on page 50
.
FF_LINE_END_F1
Address: 019h
15-10
–
Not Used.
–
–
9-0
FF_LINE_END_F1[9:0]
Field 1 Full Field end line data used to set EDH
calculation range outside of SMPTE RP 165 values.
R/W
0
Table 3-13: Host Interface Description for EDH Calculation Range Registers (Continued)
Register Name
Bit
Name
Description
R/W
Default
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS1561-CFE3 | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| GS1574A | GS1574A HD-LINX-R II Adaptive Cable Equalizer |
| GS1574ACNE3 | GS1574A HD-LINX-R II Adaptive Cable Equalizer |
| GS1574 | GS1574 HD-LINX -TM II Adaptive Cable Equalizer |
| GS1574-CNE3 | GS1574 HD-LINX -TM II Adaptive Cable Equalizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1561-CFE3 | 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru |
| GS1561-CFT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1561-CFTE3 | 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru |
| GS1563 | 制造商:Thomas & Betts 功能描述:Installing Dies |
| GS1567 | 制造商:P&B 功能描述:5945-00-9151610 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。