參數(shù)資料
型號： GS1561-CF
廠商： Gennum Corporation
英文描述： GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer
中文描述： GS1560A/GS1561的HD - LINX進程- R的第二雙率解串器
文件頁數(shù)： 13/80頁
文件大?。?/td> 842K
代理商： GS1561-CF
GS1560A/GS1561 Data Sheet
27360 - 8
September 2005
13 of 80
31
DATA_ERROR
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
The DATA_ERROR signal will be LOW when an error within the received
data stream has been detected by the device. This pin is a logical 'OR'ing
of all detectable errors listed in the internal ERROR_STATUS register.
Once an error is detected, DATA_ERROR will remain LOW until the start
of the next video frame / field, or until the ERROR_STATUS register is
read via the host interface.
The DATA_ERROR signal will be HIGH when the received data stream
has been detected without error.
NOTE:
It is possible to program which error conditions are monitored by
the device by setting appropriate bits of the ERROR_MASK register HIGH.
All error conditions are detected by default.
32
FIFO_LD
Synchronous
with PCLK
Output
CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used as a control signal for external FIFO(s).
Normally HIGH but will go LOW for one PCLK period at SAV.
33, 68
CORE_GND
–
Power
Ground connection for the digital core logic. Connect to digital GND.
34
F
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the ODD / EVEN field of the video signal.
The F signal will be HIGH for the entire period of field 2 as indicated by the
F bit in the received TRS signals.
The F signal will be LOW for all lines in field 1 and for all lines in
progressive scan systems.
35
V
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video field / frame that is used for
vertical blanking.
The V signal will be HIGH for the entire vertical blanking period as
indicated by the V bit in the received TRS signals.
The V signal will be LOW for all lines outside of the vertical blanking
interval.
36
H
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active video data.
H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register accessible via the host interface.
Active Line Blanking (H_CONFIG = 0
h
)
The H signal will be HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words, and LOW otherwise. This is the
default setting.
TRS Based Blanking (H_CONFIG = 1
h
)
The H signal will be HIGH for the entire horizontal blanking period as
indicated by the H bit in the received TRS ID words, and LOW otherwise.
37, 64
CORE_VDD
–
Power
Power supply connection for the digital core logic. Connect to +1.8V DC
digital.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料
PDF描述
GS1561-CFE3 GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer
GS1574A GS1574A HD-LINX-R II Adaptive Cable Equalizer
GS1574ACNE3 GS1574A HD-LINX-R II Adaptive Cable Equalizer
GS1574 GS1574 HD-LINX -TM II Adaptive Cable Equalizer
GS1574-CNE3 GS1574 HD-LINX -TM II Adaptive Cable Equalizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS1561-CFE3 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru
GS1561-CFT 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
GS1561-CFTE3 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru
GS1563 制造商:Thomas & Betts 功能描述:Installing Dies
GS1567 制造商:P&B 功能描述:5945-00-9151610
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*