- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384345 > GS1561-CF (Gennum Corporation) GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer PDF資料下載
參數(shù)資料
| 型號(hào)： | GS1561-CF |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| 中文描述： | GS1560A/GS1561的HD - LINX進(jìn)程- R的第二雙率解串器 |
| 文件頁(yè)數(shù)： | 11/80頁(yè) |
| 文件大?。?/td> | 842K |
| 代理商： | GS1561-CF |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)
GS1560A/GS1561 Data Sheet
27360 - 8
September 2005
11 of 80
21
SDO_EN/DIS
Non
Synchronous
Input
GS1560A
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output loop-through stage.
When set LOW, the serial digital output signals SDO and SDO are
disabled and become high impedance.
When set HIGH, the serial digital output signals SDO and SDO are
enabled.
NC
–
–
GS1561
No Connect.
22
CD_GND
–
Power
GS1560A
Ground connection for the serial digital cable driver. Connect to analog
GND.
NC
–
–
GS1561
No Connect.
23, 24
SDO, SDO
Analog
Output
GS1560A
Serial digital loop-through output signal operating at 1.485Gb/s,
1.485/1.001Gb/s, or 270Mb/s.
The slew rate of these outputs is automatically controlled to meet SMPTE
292M and 259M specifications according to the setting of the SD/HD pin.
NC
–
–
GS1561
No Connect.
25
RESET_TRST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings and to
reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW)
When asserted LOW, all functional blocks will be set to default conditions
and all input and output signals become high
impedance, including the
serial digital outputs SDO and
SDO.
Must be set HIGH for normal device operation.
NOTE: When in slave mode, reset the device after the SD/
HD
input has
been initially configured, and after each subsequent SD/HD data rate
change.
JTAG Test Mode (JTAG/HOST = HIGH)
When asserted LOW, all functional blocks will be set to default and the
JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence resumes.
26
JTAG/HOST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured as GSPI pins for normal host interface operation.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS1561-CFE3 | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| GS1574A | GS1574A HD-LINX-R II Adaptive Cable Equalizer |
| GS1574ACNE3 | GS1574A HD-LINX-R II Adaptive Cable Equalizer |
| GS1574 | GS1574 HD-LINX -TM II Adaptive Cable Equalizer |
| GS1574-CNE3 | GS1574 HD-LINX -TM II Adaptive Cable Equalizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1561-CFE3 | 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru |
| GS1561-CFT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1561-CFTE3 | 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru |
| GS1563 | 制造商:Thomas & Betts 功能描述:Installing Dies |
| GS1567 | 制造商:P&B 功能描述:5945-00-9151610 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。