參數(shù)資料
型號(hào)： GS1532-CFE3
廠商： Gennum Corporation
英文描述： GS1532 HD-LINX-TM II Multi-Rate Serializer
中文描述： GS1532的HD - LINX進(jìn)程，商標(biāo)第二多速率串行器
文件頁(yè)數(shù)： 44/52頁(yè)
文件大?。?/td> 512K
代理商： GS1532-CFE3
GS1532 Data Sheet
21498 - 6
June 2005
44 of 52
3.10.3 Configuration and Status Registers
Table 3-11
summarizes the GS1532's internal status and configuration registers.
All of these registers are available to the host via the GSPI and are all individually
addressable.
Where status registers contain less than the full 16 bits of information, two or more
registers may be combined at a single logical address.
3.11 JTAG
When the JTAG/HOST input pin of the GS1532 is set HIGH, the host interface port
will be configured for JTAG test operation. In this mode, pins 27 through 30
become TMS, TDO, TDI, and TCK. In addition, the RESET_TRST pin will operate
as the test reset pin.
Boundary scan testing using the JTAG interface will be enabled in this mode.
There are two methods in which JTAG can be used on the GS1532:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
Equipment) during PCB assembly; or
2. Under control of the host for applications such as system power on self tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other
devices driving the digital I/O pins. If the tests are to be applied only at ATE, this
can be accomplished with tri-state buffers used in conjunction with the
JTAG/HOST input signal. This is shown in
Figure 3-10
.
Table 3-11: GS1532 Internal Registers
Address
Register Name
See Section
000h
IOPROC_DISABLE
Section 3.6.3
002h
EDH_FLAG
Section 3.6.3.3
004h
VIDEO_STANDARD
Section 3.6.2
010h - 011h
VIDEO_FORMAT
Section 3.6.3.1
014h - 017h
RASTER_STRUCTURE
Section 3.6.2
018h - 025h
EDH_CALC_RANGES
Section 3.6.3.3
027h - 028h
LINE_352M
Section 3.6.3.1
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