參數(shù)資料
型號(hào)： GMS81524BT
廠商： Hynix Semiconductor Inc.
英文描述： [General Purpose(1) : ADC/ LED/ SCI/ PWM]
中文描述： [通用（1）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制]
文件頁(yè)數(shù)： 77/110頁(yè)
文件大?。?/td> 1980K
代理商： GMS81524BT
GMS81508B/16B/24B, GMS82512/16/24
74
MAY. 2001 Ver 2.0
21. POWER FAIL PROCESSOR
The GMS815xxB and GMS825xx have an on-chip power
fail detection circuitry to immunize against power noise. A
configuration register, PFDR, can enable or disable the
power fail detect circuitry. Whenever V
DD
falls close to or
below power fail voltage for 100ns, the power fail situation
may reset or freeze MCU according to PFR bit of PFDR.
Refer to “7.4 DC Electrical Characteristics” on page 16.
In the in-circuit emulator, power fail function is not imple-
mented and user can not experiment with it. Therefore, af-
ter final development of user program, this function may
be experimented or evaluated.
Note:
User can select power fail voltage level according to
PFV bit of PFDR at the OTP(GMS815xxBT/GMS825xxT)
but must select the power fail voltage level to define PFD
option of “Mask Order & Verification Sheet” at the mask
chip(GMS815xxB/GMS825xx).
Because the power fail voltage level of mask chip
(GMS815xxB/GMS825xx) is determined according to mask
option regardless of PFV bit of PFDR
Note:
If power fail voltage is selected to 3.0V on 3V oper-
ation, MCU is freezed at all the times.
Table 21-1 Power fail processor
Figure 21-1 Power Fail Voltage Detector Register
Power FailFunction
OTP
MASK
Enable/Disable
by PFD flag
by PFD flag
Level Selection
by PFV flag
by mask option
7
6
5
4
3
2
1
0
PFS
INITIAL VALUE: ---- 1100
B
ADDRESS: 0F9
H
PFDR
R/W
R/W
R/W
PFD
Operation Mode
0: Normal operation regardless of power fail
1: MCU will be reset by power fail detection
Disable Flag
0: Power fail detection enable
1: Power fail detection disable
Power Fail Status
0: Normal operate
1: Set to “1” if power fail is detected
PFR
PFV
Power Fail Voltage Selection Flag
0: 2.4V
1: 3.0V
R/W
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