參數(shù)資料
型號： GMS81524BT
廠商： Hynix Semiconductor Inc.
英文描述： [General Purpose(1) : ADC/ LED/ SCI/ PWM]
中文描述： [通用（1）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制]
文件頁數(shù)： 106/110頁
文件大小： 1980K
代理商： GMS81524BT
GMS81508B/16B/24B, GMS82512/16/24
xviii
MAY. 2001 Ver 2.0
16-Bit Operation
Bit Manipulation
NO.
MNENONIC
OP
CODE
1D
5D
BYTE
NO.
2
2
CYCLE
NO
5
4
OPERATION
FLAG
NVGBHIZC
NV - - H - ZC
N - - - - - ZC
1
2
ADDW dp
CMPW dp
16-bits add without carry : YA
←
YA + (dp+1)(dp)
Compare YA contents with memory pair contents :
YA - (dp+1)(dp)
Decrement memory pair : (dp+1)(dp)
←
{(dp+1)(dp)} - 1
Increment memory pair : (dp+1)(dp)
←
{(dp+1)(dp)} + 1
Load YA : YA
←
(dp+1)(dp)
Store YA : (dp+1)(dp)
←
YA
16-bits subtract without carry : YA
←
YA - (dp+1)(dp)
3
4
5
6
7
DECW dp
INCW dp
LDYA dp
STYA dp
SUBW dp
BD
9D
7D
DD
3D
2
2
2
2
2
6
6
5
5
5
N - - - - - Z -
N - - - - - Z -
N - - - - - Z -
- - - - - - - -
NV - - H - ZC
NO.
MNENONIC
OP
CODE
8B
8B
0C
1C
y1
2B
20
40
80
AB
AB
CB
CB
4B
6B
6B
x1
0B
A0
C0
EB
5C
3C
BYTE
NO.
3
3
2
3
2
2
1
1
1
3
3
3
3
3
3
3
2
2
1
1
3
3
3
CYCLE
NO
4
4
4
5
4
2
2
2
2
5
5
4
4
5
5
5
4
2
2
2
6
6
6
OPERATION
FLAG
NVGBHIZC
- - - - - - - C
- - - - - - - C
1
2
3
4
5
6
7
8
9
AND1 M.bit
AND1B M.bit
BIT dp
BIT !abs
CLR1 dp.bit
CLR1A A.bit
CLRC
CLRG
CLRV
EOR1 M.bit
EOR1B M.bit
LDC M.bit
LDCB M.bit
NOT1 M.bit
OR1 M.bit
OR1B M.bit
SET1 dp.bit
SETA1 A.bit
SETC
SETG
STC M.bit
TCLR1 !abs
TSET1 !abs
Bit AND C-flag : C
←
C
∧
(M.bit)
Bit AND C-flag and NOT : C
←
C
∧
(M.bit)
Bit test A with memory :
Z
←
A
∧
M, N
←
(M
7
), V
←
(M
6
)
Clear bit : (M.bit)
←
“0”
Clear A.bit : (A.bit)
←
“0”
Clear C-flag : C
←
“0”
Clear G-flag : G
←
“0”
Clear V-flag : V
←
“0”
Bit exclusive-OR C-flag : C
←
C
⊕
(M.bit)
Bit exclusive-OR C-flag and NOT : C
←
C
⊕
(M.bit)
Load C-flag : C
←
(M.bit)
Load C-flag with NOT : C
←
(M.bit)
Bit complement : (M.bit)
←
(M.bit)
Bit OR C-flag : C
←
C V (M.bit)
Bit OR C-flag and NOT : C
←
C V (M.bit)
Set bit : (M.bit)
←
“1”
Set A.bit : (A.bit)
←
“1”
Set C-flag : C
←
“1”
Set G-flag : G
←
“1”
Store C-flag : (M.bit)
←
C
Test and clear bits with A : A - (M), (M)
←
(M)
∧
(A)
Test and set bits with A : A - (M), (M)
←
(M) V (A)
MM - - - - Z -
- - - - - - - -
- - - - - - - -
- - - - - - - 0
- - 0 - - - - -
- 0 - - 0 - - -
- - - - - - - C
- - - - - - - C
- - - - - - - C
- - - - - - - C
- - - - - - - -
- - - - - - - C
- - - - - - - C
- - - - - - - -
- - - - - - - -
- - - - - - - 1
- - 1 - - - - -
- - - - - - - -
N - - - - - Z -
N - - - - - Z -
10
11
12
13
14
15
16
17
18
19
20
21
22
23
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