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參數(shù)資料
| 型號(hào)： | GMS81524BT |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | [General Purpose(1) : ADC/ LED/ SCI/ PWM] |
| 中文描述： | [通用（1）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制] |
| 文件頁(yè)數(shù)： | 68/110頁(yè) |
| 文件大?。?/td> | 1980K |
| 代理商： | GMS81524BT |
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GMS81508B/16B/24B, GMS82512/16/24
MAY. 2001 Ver 2.0
65
activated mode: rising edge, falling edge, and both edge.
Figure 16-7 External Interrupt Block Diagram
INT0 ~ INT3 are multiplexed with general I/O ports
(R40~R43). To use as an external interrupt pin, the bit of
R4 port mode register PMR4 should be set to “1” corre-
spondingly.
Example:
To use as an INT0 and INT2
:
:
;
**** Set port as an input port R40,R42
LDM
;
;
**** Set port as an external interrupt port
LDM
PMR4,#05H
;
;
**** Set Falling-edge Detection
LDM
IEDS,#0001_0001B
:
:
:
R4DD,#1111_1010B
Response Time
The INT0 ~ INT3 edge are latched into INT1IF ~ INT3IF
at every machine cycle. The values are not actually polled
by the circuitry until the next machine cycle. If a request is
active and conditions are right for it to be acknowledged, a
hardware subroutine call to the requested service routine
will be the next instruction to be executed. The DIV itself
takes twelve cycles. Thus, a minimum of twelve complete
machine cycles elapse between activation of an external
interrupt request and the beginning of execution of the first
instruction of the service routine.
Figure 16-8shows interrupt response timings.
Figure 16-8 Interrupt Response Timing Diagram
INT0IF
INT0 pin
INT0 INTERRUPT
INT1IF
INT1 pin
INT1 INTERRUPT
INT2IF
INT2 pin
INT2 INTERRUPT
IEDS
[0F8H]
INT3IF
INT3 pin
INT3 INTERRUPT
Edge selection
Register
2
2
2
2
Interrupt
goes
active
Interrupt
latched
Interrupt
processing
Interrupt
routine
8 f
XIN
max. 12 f
XIN
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