參數(shù)資料
型號: GL811S
廠商: Genesys Logic, Inc.
英文描述: USB 2.0 to ATA/ATAPI Bridge Controller
中文描述: USB 2.0至的ATA / ATAPI控制器橋
文件頁數(shù): 20/37頁
文件大?。?/td> 958K
代理商: GL811S
GL811S USB2.0 to ATA/ATAPI Bridge Controller
2007 Genesys Logic Inc. - All rights reserved.
Page 20
All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown
towards the bottom of the page relative to the asserted condition.
The interface uses a mixture of negative and positive signals for control and data. The terms asserted and
negated are used for consistency and are independent of electrical characteristics.
In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. The following
illustrates the representation of a signal named Test going from negated to asserted and back to negated, based
on the polarity of the signal.
-
Signal transition (asserted or negated)
-
Data transition (asserted or negated)
-
Data valid
-
Undefined but not necessarily released
-
Asserted, negated or released
-
Released
-
The “other” condition if a signal is shown with no change
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