
GL811S USB2.0 to ATA/ATAPI Bridge Controller
2007 Genesys Logic Inc. - All rights reserved.
Page 19
6.3.2 D+/ D-
Table 6.4 - D+/ D-
Parameter
Min.
Typ.
Max.
Unit
D+/D- static output LOW (R
L
of 1.5K to V
CC
)
0
0.3
V
D+/D- static output HIGH (R
L
of 15K to GND )
2.8
3.6
V
Differential input sensitivity
0.2
V
Single-ended receiver threshold
0.8
2.0
V
Transceiver capacitance
20
pF
Hi-Z state data line leakage
-10
+10
μ
A
Driver output resistance
28
43
Ohms
6.3.3 Switching Characteristics
Table 6.5 - Switching Characteristics
Parameter
Min.
Typ.
Max.
Unit
X1 crystal frequency
11.97
12
12.03
MHz
X1 cycle time
83.3
ns
D+/D- rise time with 50pF loading
4
20
ns
D+/D- fall time with 50pF loading
4
20
ns
6.4 AC Characteristics- ATA/ ATAPI
The GL811S complies with ATA / ATAPI-6 specification rev 1.0, which supports following data transfer modes:
1.
DMA (Direct Memory Access) data transfer:
DMA data transfer means of data transfer between device and host memory without host processor
intervention.
-
Multiword DMA: Multiword DMA is a data transfer protocol used with the READ DMA, WRITE
DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When a
Multiword DMA transfer is enabled as indicated by IDENTIFY DEVICE or IDENTIFY PACKET
DEVICE data, this data transfer protocol shall be used for the data transfers associated with these
commends. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.)
-
Ultra DMA: Ultra DMA Is a data transfer protocol used with the READ DMA, WRITE DMA,
READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When this protocol is
enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these
commands are issued by the host. This protocol applies to the Ultra DMA data burst only. (Please
refer to the ATA / ATAPI-6 specification rev 1.0 for more information.)
Following listed the symbols and their respective definitions that are used in the timing diagram: