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參數(shù)資料
| 型號： | GL310MC4D |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GL310MC PS/2 4D Mouse Controller |
| 中文描述： | GL310MC的PS / 2 4D滑鼠控制器 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 232K |
| 代理商： | GL310MC4D |
Revision 1.0 July/16/1998
6
GL310MC PS/2 4D Mouse Controller
l
Inhibit.
If the host is holding CLK low, the device is inhibited from transmitting data.
However, internal mouse processing continues to occur.
l
Request to send.
If the host is holding DATA low and CLK high, it is ready to transmit a
command or argument byte to the device.
4.3 Output to host
The device can transmit a byte to the host whenever the bus is idle. If the bus is inhibited, the device
waits for it to leave the inhibit state before transmitting. If there is a host request-to-send, the device
receives and processes the host command byte rather than transmitting its own data.
If the host holds CLK low (inhibit) during a transmission, the device will recognize this within 100
μ
s
and abort the transmission. The device recognizes an inhibit by noting that CLK remains low during
the high portion of the clock cycle. If the inhibit occurs before the rising edge of the tenth clock (the
parity bit), the transmission is cancelled and will be retried as soon as the inhibit is released. (An
ACK ($FA) reply to an incoming command or argument byte is simply thrown away if cancelled,
although the command being acknowledged is not cancelled.) If the inhibit begins after the tenth
clock, the transmission is considered complete and the host must accept the transmitted byte. The
host may hold CLK low after the transmission, effectively extending clock 11, to inhibit the device
while it processes the transmission.
In Figure 4-2, the CLK signal is low for 30-50
μ
s (t1) and high for 30-50
μ
s (t2) in each bit cell.
DATA will be valid at least 5
μ
s before the falling edge (t3) and at least 5
μ
s after the rising edge (t4)
of the clock.
4.3.1 Input from host
The host signals its intent to transmit a command or argument byte by holding CLK low for at
least 60
μ
s, them pulling DATA low and releasing CLK, thus putting the bus into the host request-
to-send state. The device checks for this state at least every 10ms (t5). When the device detects a
request-to-send, it pulses CLK low 11 times to receive a byte. The host can abort the transmission
midway through by holding CLK low for at least 100
μ
s.
After the tenth clock, the device checks for a valid stop bit (DATA line high), and responds by
pulling DATA low and clocking one more time (the "line control bit"). The host can then hold
CLK low within 50
μ
s (t12) to inhibit the device until the host is ready to receive the reply. If the
device finds DATA low during the stop bit, a framing error has occurred; the device continues to
clock until DATA goes high, then sends a Resend to the host as described below.
Figure 4-2. PS/2 output waveforms
t1
t2
t3
t4
Start bit
Bit0
Bit1
Bit7
Parity bit
Stop bit
CLK1
CLK2
CLK3
CLK9
CLK10
CLK11
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