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參數(shù)資料
| 型號： | GL310MC4D |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GL310MC PS/2 4D Mouse Controller |
| 中文描述： | GL310MC的PS / 2 4D滑鼠控制器 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 232K |
| 代理商： | GL310MC4D |
Revision 1.0 July/16/1998
5
GL310MC PS/2 4D Mouse Controller
4.
PS/2 Protocol
The PS/2 protocol allows synchronous, bi-directional serial communication between the host and the
device. Either side may transmit a command or data byte at any time, although only one side can
transmit at one time. During initialization, the host sends command bytes to the device. Some
commands are followed by argument bytes. The device acknowledges each command and argument
byte with an ACK ($FA) byte, possibly followed by one or more data bytes. If the host has enabled
"Stream mode" transmission, then the device may send spontaneous data packets to the host describing
finger motions and button state changes.
4.1 Electrical interface
The PS/2 protocol includes two signal wires as well as +5V power and ground. The signal wires,
CLK and DATA, are bi-directional "open-collector" signals; they are normally held at a high (+5V)
level by a 5-10K pull-up resistor on the host, but either the host or the Mouse device can pull them
low at any time. When the port is idle, both signal wires are floating high. The host can inhibit the
device at any time by holding the CLK wire low.
Note that neither side ever actively pulls CLK or DATA high; to output a logic 1, the wire is left
undriven and allowed to float high.
The following diagram shows the interconnections between the host and the PS/2 mouse device:
4.2 Byte transmission
Each byte transmitted between the device and the host includes a start bit ( a logic 0), eight data bits
(LSB first), a parity bit (odd parity), and a stop bit (a logic 1). Odd parity means the eight data bits
and the parity bit together contain an odd number of 1's . During transmission , the device pulses the
CLK signal low for each of the 11bits, while either the host or the device pulls the DATA wire low to
signal a logic 0 or allows DATA to float high to signal a logic 1.
Between transmissions, the bus can be in one of three states:
l
Idle.
If CLK and DATA are both high, there is no activity on the bus.
Host Computer
PS/2 Mouse
Left
Right
CLK
DATA
CLK
DATA
Figure 4-1. PS/2 system diagram
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