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參數(shù)資料
| 型號(hào)： | GF9331 |
| 英文描述： | GF9331 - HDTV/SDTV Motion Co-processor |
| 中文描述： | GF9331 -高清/標(biāo)清運(yùn)動(dòng)協(xié)處理器 |
| 文件頁數(shù)： | 13/34頁 |
| 文件大小： | 550K |
| 代理商： | GF9331 |
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GENNUM CORPORATION
18283 - 3
13
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2.2.4 V_OFFSET_ODD
This defines the number of lines from the V_IN pin EAV
transition to the end of the odd active video field region.
This parameter has a maximum value of 255. Eight bits
within the host interface are dedicated to this parameter.
This parameter has been added to accommodate all video
decoders which that output non-standard timing for the
V_IN signal. See Figure 3.
2.2.5 V_OFFSET_EVEN
This parameter defines the number of lines from the
V_IN pin EAV transition to the end of the even active video
field region. This parameter has a maximum value of 255.
Eight bits within the host interface are dedicated to this
parameter.
This
parameter
accommodate all video decoders that output non-standard
timing for the V_IN signal. See Figure 3.
has
been
added
to
2.2.6 F_OFFSET_ODD
This defines the number of lines from the F_IN pin EAV
transition to the vertical blanking interval following the odd
field. This parameter has a maximum value of 255. Eight
bits within the host interface are dedicated to this
parameter.
This
parameter
accommodate all video decoders that output non-standard
timing for the F_IN signal. See Figure 2.
has
been
added
to
2.2.7 F_OFFSET_EVEN
This register defines the number of lines from the F_IN pin
EAV transition to the vertical blanking interval following the
even field. This parameter has a maximum value of 255.
Eight bits within the host interface are dedicated to this
parameter.
This
parameter
accommodate all video decoders which output non-
standard timing for the F_IN signal. See Figure 2.
has
been
added
to
2.2.8 H_POLARITY
This register defines the polarity of the H_IN pin. With
H_POLARITY set LOW, a falling transition on the H_IN pin
indicates end of active video. With H_POLARITY set HIGH,
a rising transition on the H_IN pin indicates the end of
active video. One bit within the host interface is dedicated
to this parameter.
2.2.9 F_POLARITY
This register defines the polarity of the F_IN pin. Refer to
Table 2 for F_POLARITY encoding. One bit within the host
interface is dedicated to this parameter.
2.2.10 V_POLARITY
This register defines the polarity of the V_IN pin. With
V_POLARITY set LOW, a falling transition on the V_IN pin
indicates the end of active video. With V_POLARITY set
HIGH, a rising transition on the V_IN pin indicates the end of
active video. One bit within the host interface is dedicated to
this parameter.
3.
SEAMLESS INTERFACE TO THE GF9331 MOTION
CO-PROCESSOR FOR DIRECTIONAL FILTER CONTROL
The GF9330 can operate as a stand-alone motion adaptive
de-interlacer or can operate in conjunction with the GF9331
Motion Co-processor. The GF9331 contains adaptive
multi-directional edge detection and vertical motion
detection. Control signals are fed back directly to the
GF9330.
These control signals adaptively switch the GF9330
’
s
internal edge & vertical motion de-interlacing filters on a
pixel by pixel basis. These control signals are fed to the
GF9330 by the GF9331 over the FIL_SEL[3:0] control bus.
When the GF9330 is not being used with the GF9331, the
FIL_SEL[3:0] inputs should be set LOW.
NOTE:
When using the GF9331, the Y_IN[9:0] of the
GF9330 must be connected to Y_OUT[9:0] of the GF9331
and C_IN[9:0] of the GF9330 must be connected to the
C_OUT[9:0] of the GF9331. FIL_SEL[3:0] of the GF9330
must also be connected to FIL_SEL[3:0] of the GF9331.
The timing information from the GF9331 is provided
exclusively through the F_OUT, H_OUT and V_OUT pins
which must be connected to the F_IN, H_IN and V_IN pins
of the GF9330.
4. SEAMLESS INTERFACE TO EXTERNAL SDRAMS
For all SD video formats, the GF9330 requires two
1M x 24-bit (min) SDRAM field buffers.
To pass HD video formats in bypass mode, the GF9330
requires two field buffers, each implemented with a 1M x
48-bit (min) SDRAM configuration. To deinterlace HD
formats the memory requirements increase to a 4M x
48-bit (min) SDRAM configuration. This configuration
supports all HD and SD operational modes. The following
external SDRAM devices are supported for the external
field buffer function.
NEC: uPD4516161AG5, uPD4564163G5,
uPD45128163G5
Micron: MT48LC4M16A2, MT48LC8M16A2
Samsung: K4S161622C, K4S641632C, K4S281632B
TABLE 2: F_POLARITY
F_POLARITY
REGISTER
F PIN
F PIN FUNCTION
0
0
Even Field
0
1
Odd Field
1
0
Odd Field
1
1
Even Field
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相關(guān)代理商/技術(shù)參數(shù) |
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| GF9331-CBP | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:DTV/SDTV Motion Co-processor |
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| GF9452A-CBE3 | 制造商:Sigma Designs 功能描述:IC VIDEO PROCESSOR 12BIT 725HSBG |
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