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參數(shù)資料
| 型號(hào)： | GCIXF1002EDT |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 126/128頁(yè) |
| 文件大小： | 1262K |
| 代理商： | GCIXF1002EDT |
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Intel
IXF1002 Dual Port Gigabit Ethernet Controller
126
Datasheet
Note that when the IXF1002 is not in Multi-Packet Mode, the device retains all of the features as
described in the IXF1002 Data Sheet.
C.3
Multi-Packet Mode
In order to enable systems that require a high serial transmit threshold to reach full wire speed
operation, Multi-Packet Mode was introduced. When this mode is enabled
(PORT_MODE<14:13> = 1), up to 16 full packets may be stored in the IXF1002
’
s TFIFO.
In Multi-Packet Mode, txrdy signal deassertion rules are changed to indicate at least one of the
following:
The amount of free space in the TFIFO is below the FIFO transmit threshold
(FFO_TSHD<TTH>).
The number of full packets stored in the TFIFO is sixteen.
A data burst across the IX Bus is in progress.
While working in Multi-Packet Mode, the following IXF1002 features are not supported:
The ability to add, strip or change VLAN tags during packet transmission
TFIFO packet count status information (TX_RX_STT<PKC>). Reading this register will
give an incorrect value.
Minimum packet sizes of less than 32 bytes on the IX Bus. Packets that have less than 32
bytes between SOP and EOP may corrupt previous and/or following packets.
Single packet mode for the TFIFO (TX_RX_PARAM<SPM>).
The functionality of txasis when asserted together with SOP (no padding and/or CRC
appended to the packet even if the port was programmed to do so) at IX Bus frequencies below
50 MHz. Note
that txasis functionality works as specified in the IXF1002 Data Sheet for frequencies of 50
MHz or higher.
C.4
Port Working Mode Register
Mnemonic: PORT_MODE
Address: 24H
–
25H
The port mode register controls the CPU bus, IX Bus, and serial interface modes of work.
Note:
Bits 14, 13, 12, 11, 2, and 0 must have the same value in both ports.
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