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參數(shù)資料
| 型號： | GCIXF1002EC |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 82/128頁 |
| 文件大?。?/td> | 1262K |
| 代理商： | GCIXF1002EC |
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Intel
IXF1002 Dual Port Gigabit Ethernet Controller
82
Datasheet
6.5
MAC Receive Operation
This section describes the detailed receive operation as supported by the IXF1002. Receive
activities are registered into network management registers, which are accessible through the CPU
port.
6.5.1
Receive Initiation
The IXF1002 continuously monitors the network when reception is enabled. When an activity is
recognized, the IXF1002 starts to process the incoming data.
In the GMII mode, the IXF1002 detects activity when the data valid signal (dv{i}) asserts. In
GPCS mode, the IXF1002 detects activity when the /S/ symbol appears. After detecting receive
activity on the line, the IXF1002 starts to process the preamble bytes.
6.5.2
Preamble Processing
The IEEE 802.3 Standard allows a maximum size of 56 bits (7 bytes) for the preamble, while the
IXF1002 allows any arbitrary preamble length. The IXF1002 checks for the start frame delimiter
(SFD) byte. If the next byte of the preamble which is different from 1010 1010, is not 1010 1011,
the frame will be discarded. In this case the IXF1002 waits until the network activity stops before
monitoring the network activity for a new preamble.
The interpacket gap (IPG) between received frames should be at least 80-bit time.
6.5.3
Frame Decapsulation
While the frame is being assembled, the IXF1002 continues to monitor the line condition.
In the GMII mode, the IXF1002 detects the end of frame when the data valid signal (dv{i})
deasserts. In GPCS mode, the IXF1002 detects the end of the frame when the /T/ symbol appears.
Reception terminates with a frame error if the frame is not a valid MAC frame (e.g. short, too long,
no SFD), or if a receive error was detected during frame reception.
In the GMII mode, receive error is detected when the receive error signal (rerr{i}) asserts during
frame reception. In GPCS mode, receive error is detected when a symbol error is detected. The
IXF1002 refers to the last 4 bytes received as the CRC. It checks the CRC bytes of all received
frames and reports all errors.
6.5.4
Terminating Reception
When reception terminates, the IXF1002 determines the status of the received frame and loads the
status into the receive FIFO. The IXF1002 can report the following events at the end of frame
reception:
Overflow
The IXF1002 receive FIFO is not emptied as rapidly as it is filled, and the frame data is lost. If
the FIFO is already full when a new frame is received, it will not be loaded in the FIFO and the
whole packet is lost.
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| GCIXF1002ED | 功能描述:IC 2PORT GIGBIT ETHNT MAC 304BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| GCIXF1002EDT | 制造商:Intel 功能描述:Ethernet CTLR Single Chip 1000Mbps 3.3V 304-Pin ESBGA |
| GCIXF1012EC.A3-884560 | 功能描述:IC ETHERNET MAC 12PORT 672-BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
| GCIXF1012ECA3 | 制造商:Cortina Systems Inc 功能描述: 制造商:Intel 功能描述: |
| GCIXF1024EC.A3-884561 | 功能描述:IC ETHERNET MAC 24PORT 672-BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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