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參數(shù)資料
| 型號： | GCIXF1002EC |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 73/128頁 |
| 文件大?。?/td> | 1262K |
| 代理商： | GCIXF1002EC |
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Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
73
5.0
CPU Interface Operation
The following sections describe the CPU interface operation.
5.1
CPU Interface
The IXF1002 has a dedicated port for a CPU interface, enabling access to the different registers
without interfering packet transfer through the FIFOs. The CPU interface is generic and supports a
wide range of standard controllers. Each of the two IXF1002 ports has its own independent registers.
Each of the port registers is accessible through an 8/16-bit-wide data bus and a 10-bit-wide address
bus. A specific port is addressed by using the port select signal (cps), which may be considered a part
of the address bus. Each port has a dedicated interrupt signal (cint_l_{i}) to report special events to
the CPU.
The IXF1002 supports two CPU data bus widths: 8 (default) and 16 bit (controlled by the
PORT_MODE<CPUBW> bit). In 16 bit mode, registers are accessible only through an even
numbered address. In 8 bit mode, each byte is accessed independently through its individual
address.
Each control and status register is 2 bytes wide. Network statistic counters are 4 bytes or 6 bytes
wide and require multiple CPU accesses to be fully read.
5.2
Network Management
The IXF1002 includes statistic counters defined by Ethernet SNMP MIB and RMON MIB
standards. Each event counter is 4 byte wide and each byte counter is 6 byte wide.
To assemble each counter value, its bytes must be read from the lower to the upper addresses.
Each counter is accessible through two different addresses. One address will cause the read bytes to
reset, while the other will not. When a counter overflows, it resets automatically, causes the
corresponding bit in the counter overflow status registers (TX_OV_STT and RX_OV_STT) to
assert, and can generate an interrupt if programmed accordingly (see
Section 3.2.2.2
and
Section
3.2.3.12
).
Partial byte reading is also possible. If the exact counter value is not required, the lower counter
bytes may not be read. If the counter is read often through an address that reset its count (with a
100H offset), the upper byte will always remain null and may not be read.
Receive statistic counters are updated according to analysis of the received packet, while ignoring
the IXF1002 filtering mode or the receive FIFO status. When the port is in the disable mode, the
counters are not updated.
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