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參數(shù)資料
| 型號： | G12290EJ2V0AN00 |
| 英文描述： | uPC1663 DC to VHF Wideband Differential Input and Output Amplifier IC |
| 中文描述： | uPC1663直流高頻寬帶差分輸入和輸出功放IC |
| 文件頁數(shù)： | 13/23頁 |
| 文件大?。?/td> | 165K |
| 代理商： | G12290EJ2V0AN00 |
13
OUT
1
+ OUT
2
2
3.11 Supply Voltage Rejection Ratio (SVR)
This indicates the rate of variation in the input conversion offset relative to the supply voltage.
This can be expressed as follows, based on the circuit shown in Figure 8.
'
V
SVR = 20 log
'
V
O
+
x
A
VD
Figure 8. Supply Voltage Rejection Ratio Measurement Circuit (V
+
side)
50
V
CC+
±
V
CC–
V
O =
OUT
1
+
OUT
2
V
+
50
6
5
3
1
8
4
3.12 Output Offset Voltage (V
O(off)
)
This indicates the DC voltage difference between both outputs when both of the differential inputs voltage is not
applied.
V
O(off)
= |OUT
1
– OUT
2
|
3.13 Output Common Mode Voltage (V
O(CM)
)
This indicates the average value from both output’s DC voltages when both of the differential inputs voltage is not
applied.
V
O(CM)
=
3.14 Output Voltage Swing (V
Op-p
)
This indicates the maximum amplitude (swing) that occurs without distortion, mainly in the output common mode
voltage.
3.15 Output Sink Current
This indicates the sink current capacity of transistors Q
10
and Q
11
. If a current that exceeds this value is accepted,
the output voltage swing is greatly reduced.
3.16 Power Supply Current
This indicates the circuit current and does not include the output load current.
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