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參數(shù)資料
| 型號： | FXLA0104QFX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | TRANSLATOR 4BIT DUAL 12-UMLP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 邏輯功能： | 變換器，雙向，3 態(tài) |
| 位數(shù)： | 4 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 數(shù)據(jù)速率： | 140Mbps |
| 通道數(shù)： | 1 |
| 輸出/通道數(shù)目： | 4 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 4ns |
| 電源電壓： | 1.1 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXLA0104
Rev. 1.0.1
12
FXLA0
1
0
4
—
Low
-V
o
ltage
Dua
l-
S
upply
4
-Bit
Vol
tage
Tra
n
s
la
to
r
I/O Architecture Benefit
The FXLA0104 I/O architecture benefits the end user,
beyond level translation, in the following three ways:
Auto Direction without an external direction pin.
Drive Capacitive Loads. Automatically shifts to a
higher current drive mode only during “Dynamic Mode”
or HL / LH transitions.
Lower Power Consumption. Automatically shifts to
low-
power mode during “Static Mode” (no transitions),
lowering power consumption.
The FXLA0104 does not require a direction pin. Instead,
the I/O architecture detects input transitions on both
side and automatically transfers the data to the
corresponding output. For example, for a given channel,
if both A and B side are at a static LOW, the direction
has been established as A B, and a LH transition
occurs on the B port; the FXLA0104 internal I/O
architecture automatically changes direction from A B
to B A.
During HL / LH transitions, or “Dynamic Mode,” a strong
output driver drives the output channel in parallel with a
weak
output
driver.
After
a
typical
delay
of
approximately 10 ns
– 50 ns, the strong driver is turned
off, leaving the weak driver enabled for holding the logic
state of the channel. This weak driver is called the “bus
hold.” “Static Mode” is when only the bus hold drives the
channel. The bus hold can be over ridden in the event of
a direction change. The strong driver allows the
FXLA0104 to quickly charge and discharge capacitive
transmission lines during dynamic mode. Static mode
conserves power, where ICC is typically < 5 A.
Bus Hold Minimum Drive Current
Specifies the minimum amount of current the bus hold
driver can source/sink. The bus hold minimum drive
current (IIHOLD) is VCC dependent and guaranteed in the
DC Electrical tables. The intent is to maintain a valid
output state in a static mode, but that can be overridden
when an input data transition occurs.
Bus Hold Input Overdrive Drive Current
Specifies the minimum amount of current required (by
an external device) to overdrive the bus hold in the
event of a direction change. The bus hold overdrive
(IIODH, IIODL) is VCC dependent and guaranteed in the DC
Electrical tables.
Dynamic Output Current
The strength of the output driver during LH / HL
transitions is referenced on page 8, Dynamic Output
Electrical Characteristics, IOHD, and IOLD.
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