- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370261 > FW82439TX Controller Miscellaneous - Datasheet Reference PDF資料下載
參數(shù)資料
| 型號(hào)： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 9/102頁 |
| 文件大?。?/td> | 759K |
| 代理商： | FW82439TX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁
Extended Temperature 82439TX (MTXC) Datasheet
9
PRELIMINARY
2.0.
SIGNAL DESCRIPTION
This section provides a detailed description of each signal. The signals are arranged in functional groups
according to their associated interface.
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal
is at a low voltage level. When “#” is not present after the signal name, the signal is asserted when at the high
voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a
mixture of “active low” and “active high” signal. The term assert, or assertion indicates that a signal is active,
independent of whether that level is represented by a high or low voltage. The term negate, or negation
indicates that a signal is inactive.
The I/O buffer types are shown below:
Buffer Type
I
O
I/O
s/t/s
od
3.3V/2.5V
Description
input only signal
totem pole output
bi-direction, tri-state input/output pin
sustained tri-state
open drain
Indicates the buffer is 3.3V or 2.5V only, depending on the voltage (3.3V or 2.5V) connected
to VccX pins.
Indicates that the output is 3.3V and input is 3.3V receiver with 5V tolerance.
Indicates 3.3V receiver with 5V tolerance.
3.3V/5V
5V
2.1.
MTXC Signals
2.1.1.
HOST INTERFACE
Name
Type
Description
A[31:3]
I/O
3.3V/2.5V
Address Bus.
A[31:3] connects to the address bus of the CPU. During CPU
cycles A[31:3] are inputs. The MTXC drives A[31:3] during inquire cycles on
behalf of PCI initiators. Bits A[31:26] act as inputs when RST# is active
BE[7:0]#
I
3.3V/2.5V
Byte Enables.
The CPU byte enables indicate which byte lane the current
CPU cycle is accessing. All eight byte lanes must be provided to the CPU if
the cycle is a cacheable read regardless of the state of BE[7:0]#.
ADS#
I
3.3V/2.5V
Address Status.
CPU asserts ADS# in T1 of the CPU bus cycle.
BRDY#
O
3.3V/2.5V
Bus Ready.
The MTXC asserts BRDY# to indicate to the CPU that data is
available on reads or has been received on writes.
NA#
O
3.3V/2.5V
Next Address.
This signal is asserted by the MTXC to indicate to the
Processor that it is ready to process a second cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FW82815 | Controller Miscellaneous - Datasheet Reference |
| FWA-25A10F | Fuse |
| FWA-30A10F | Fuse |
| FWA-35A21F | Fuse |
| FWA-40A21F | Fuse |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82439TX S L28T | 制造商:Intel 功能描述:System Controller 324-Pin BGA |
| FW82439TX S L3BT | 制造商:Intel 功能描述:System Controller |
| FW82439TX S L28T | 制造商:Intel 功能描述: |
| FW82439TX S L3BT | 制造商:Intel 功能描述:System Controller |
| FW82439TXSL28T | 功能描述:IC 82439TX SYS CTRL MTXC 324BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。