參數(shù)資料
型號: FW82439TX
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù): 31/102頁
文件大?。?/td> 759K
代理商: FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
31
PRELIMINARY
3.1.16.
CEC
EXTENDED CACHE CONTROL REGISTER
Address Offset:
Default Value:
Access:
53h
14h
Read/Write, Read Only
This 8-bit register defines the refresh rate (in HCLKs) for a DRAM CACHE L2 cache implementation, if
enabled.
Bit
Description
7:6
5
4:0
Reserved
DRAM CACHE L2 Present (ML2)
RO.
When ML2=1, an L2 DRAM CACHE is present.
DRAM Cache L2 Refresh Timer (MCRT)
R/W.
These bits determine the time the MTXC
remains idle during a DRAM cache refresh sequence. The smallest value for the MRCT must be
04h; otherwise, the MTXC will not function properly
.
The default value sets the timer refresh to 20
HCLKs. During normal operation, the value programmed into register offset 53h should not be
changed from its default value of 14h.
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