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參數(shù)資料
| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 53/102頁 |
| 文件大?。?/td> | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
53
PRELIMINARY
Seven Programmable Attribute Map (PAM) Registers are used to specify the cacheability, PCI enable, and
read/write status of the memory space between 640 Kbytes and 1 Mbytes. Each PAM Register defines a
specific address area enabling the system to selectively mark specific memory ranges as cacheable, read
only, write only, read/write, or disabled. When a memory range is disabled, all CPU accesses to that range
are forwarded to PCI.
The MTXC also supports one of two memory holes, either from 512 KB–640 KB or from 14/15 MB–16 MB in
main memory. Accesses to the memory holes are forwarded to PCI. The memory hole can be
enabled/disabled through the DRAM Control register. All other memory from 1M to 256 MB is read/write L1
cacheable, and is L2 cacheable up to 64 MB.
An optional Extended SMRAM DRAM memory space is also supported in the 256-MB to 512-MB address
range. It consists of the 640-KB–1-MB DRAM area aliased at the 256-MB memory segment, and also an
optional 128K/256K/512K/1M DRAM area chopped from the Top-of-DRAM memory and aliased above 256
MB in a similar manner.
4.3.1.
DRAM ORGANIZATION
The MTXC integrates a DRAM controller that supports EDO, FPM, and SDRAM. SDRAM, EDO and FPM
DRAM’s can be mixed between rows, however, a given row must contain only one type of DRAM. When
DRAM types are mixed (EDO, FPM and SDRAM) each row will run optimized for that particular type of
DRAM.
The MTXC supports six rows of memory (six RAS#/CS# lines). For maximum memory flexibility and
performance, it is recommended that a DRAM configuration of four rows be used. This allows 64-Mbit DRAM
devices to be used as well as the mixing of SDRAM and EDO/FPM. Figure 6 shows an EDO/FPM
configuration using x32 SIMM modules and Figure 7 shows a four row EDO/FPM/SDRAM configuration using
x64 DIMM modules (or x64 SO-DIMM).
NOTE
It is not recommended to mix SDRAM (which are 3V devices) with 5V EDO/FPM SIMMs, unless the
SDRAM and EDO/FPM are properly isolated (e.g., isolate the memory data lines with Qswitches).
Mixing 5V and 3V memory is not recommend for reliability reasons. Not all SDRAMs are 5V tolerant.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| FW82439TX S L28T | 制造商:Intel 功能描述: |
| FW82439TX S L3BT | 制造商:Intel 功能描述:System Controller |
| FW82439TXSL28T | 功能描述:IC 82439TX SYS CTRL MTXC 324BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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