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參數(shù)資料
| 型號： | FW801 |
| 英文描述： | One-Cable Transceiver/Arbiter Device |
| 中文描述： | 一個電纜收發(fā)器/仲裁器裝置 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大小： | 369K |
| 代理商： | FW801 |
Agere Systems Inc.
7
Data Sheet, Rev. 1
June 2001
One-Cable Transceiver/Arbiter Device
FW801 PHY
IEEE
1394A
Signal Information
(continued)
Table 1. Signal Descriptions
(continued)
Pin
Signal
*
Type
Name/Description
1
CTL0
I/O
Control I/O.
The CTLn signals are bidirectional communications control
signals between the PHY and the LLC. These signals control the passage
of information between the two devices. Bus-keeper circuitry is built into
these terminals.
Data I/O.
The Dn signals are bidirectional and pass data between the
PHY and the LLC. Bus-keeper circuitry is built into these terminals.
2
CTL1
3, 4, 6, 7,
8, 9, 10,
11
19
D[0:7]
I/O
/ISO
I
Link Interface Isolation Disable Input (Active-Low).
/ISO controls the
operation of an internal pulse differentiating function used on the
PHY-LLC interface signals, CTLn and Dn, when they operate as outputs.
When /ISO is asserted low, the isolation barrier is implemented between
PHY and its LLC (as described in Annex J of
IEEE
1394-1995).
/ISO is normally tied high to disable isolation differentiation. Bus-keepers
are enabled when /ISO is high (inactive) on CTL, D, and LREQ. When
/ISO is low (active), the bus-keepers are disabled. Please refer to Agere’s
application note AP98-074CMPR for more information on isolation.
Link Power Status.
LPS is connected to either the V
DD
supplying the
LLC or to a pulsed output that is active when the LLC is powered for the
purpose of monitoring the LLC power status. If LPS is inactive for more
than 1.2
μ
s and less than 25
μ
s, interface is reset. If LPS is inactive for
greater than 25
μ
s, the PHY will disable to save power. FW801 continues
its repeater function.
Link Request.
LREQ is an output from the LLC that requests the PHY to
perform some service. Bus-keeper circuitry is built into this terminal.
Powerdown.
When asserted high, PD turns off all internal circuitry except
the bias-detect circuits that drive the CNA signal.
Power for PLL Circuit.
PLLV
DD
supplies power to the PLL circuitry
portion of the device.
Ground for PLL Circuit.
PLLV
SS
is tied to a low-impedance ground
plane.
Current Setting Resistor.
An internal reference voltage is applied to a
resistor connected between R0 and R1 to set the operating current and
the cable driver output current. A low temperature-coefficient resistor
(TCR) with a value of 2.49 k
±
1% should be used to meet the
IEEE
1394-1995 standard requirements for output voltage limits.
Reset (Active-Low).
When /RESET is asserted low (active), a bus reset
condition is set on the active cable ports and the internal logic is reset to
the reset start state. An internal pull-up resistor, which is connected to
V
DD
, is provided, so only an external delay capacitor in parallel with a
resistor is required to ensure that the capacitor is discharged when PHY
power is removed. This input is a standard logic buffer and can also be
driven by an open-drain logic output buffer.
Test Mode Control.
SE is used during the manufacturing test and should
be tied to V
SS
.
Test Mode Control.
SM is used during the manufacturing test and should
be tied to V
SS
.
14
LPS
I
48
LREQ
I
18
PD
I
41
PLLV
DD
—
42
PLLV
SS
—
37
R0
I
38
R1
45
/RESET
I
23
SE
I
24
SM
I
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
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