參數(shù)資料
型號(hào)： FW801
英文描述： One-Cable Transceiver/Arbiter Device
中文描述： 一個(gè)電纜收發(fā)器/仲裁器裝置
文件頁(yè)數(shù)： 6/22頁(yè)
文件大?。?/td> 369K
代理商： FW801
6
Agere Systems Inc.
Data Sheet, Rev. 1
June 2001
One-Cable Transceiver/Arbiter Device
FW801 PHY
IEEE
1394A
Signal Information
5-7302.b (F)
Note: Active-low signals are indicated by “/” at the beginning of signal names, within this document.
Figure 2. Pin Assignments
Table 1. Signal Descriptions
Pin
Signal
*
Type
Name/Description
17
C/LKON
I/O
Bus Manager Capable Input and Link-On Output.
On hardware reset, this pin is
used to set the default value of the contender status indicated during self-ID. The
bit value programming is done by tying the signal through a 10 k
resistor to V
DD
(high, bus manager capable) or to GND (low, not bus manager capable). Using
either the pull-up or pull-down resistor allows the link-on output to override the input
value when necessary.
After hardware reset, this pin is set as an output, C/LKON indicates the reception of
a link-on message by asserting a 6.114 MHz signal.
Cable-Not-Active Output.
CNA is asserted high when none of the PHY ports are
receiving an incoming bias voltage. This circuit remains active during the power-
down mode.
Cable Power Status.
CPS is normally connected to the cable power through a
400 k
resistor. This circuit drives an internal comparator that detects the presence
of cable power. This information is maintained in one internal register and is avail-
able to the LLC by way of a register read (see
IEEE
P1394a Draft 2.0 Standard for
a High Performance Serial Bus (Supplement)).
13
CNA
O
20
CPS
I
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
12
11
10
9
8
6
5
4
3
2
1
7
AGERE FW801
V
SS
D7
D6
D5
D4
D2
V
DD
D1
D0
CTL1
CTL0
D3
25
26
27
28
29
31
32
33
34
35
36
30
V
DDA
V
SSA
V
SSA
TPB0–
TPB0+
TPA0+
TPBIAS0
V
DDA
V
DDA
V
SSA
V
SSA
TPA0–
3
3
3
4
4
4
4
4
4
4
4
4
R
R
V
D
V
S
P
D
X
X
/
S
V
S
L
P
S
1
1
1
1
1
1
2
2
2
2
2
1
C
L
V
S
V
D
C
/
C
V
S
V
D
S
S
P
PIN #1 IDENTIFIER
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