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參數(shù)資料
| 型號： | FW801 |
| 英文描述： | One-Cable Transceiver/Arbiter Device |
| 中文描述： | 一個電纜收發(fā)器/仲裁器裝置 |
| 文件頁數(shù)： | 19/22頁 |
| 文件大小： | 369K |
| 代理商： | FW801 |
Agere Systems Inc.
19
Data Sheet, Rev. 1
June 2001
One-Cable Transceiver/Arbiter Device
FW801 PHY
IEEE
1394A
Internal Register Configuration
(continued)
Table 9. PHY Register Fields for the Cable Environment
(continued)
The port status page is used to access configuration and status information for each of the PHY’s ports. The port is
selected by writing zero to Page_select and the desired port number to Port_select in the PHY register at address
0111
2
. The format of the port status page is illustrated by Table 10 below; reserved fields are shown shaded. The
meanings of the register fields with the port status page are defined by Table 11.
Table 10. PHY Register Page 0: Port Status Page
Field
Size Type
Power Reset
Value
Description
Enab_accel
1
rw
0
Enable Arbitration Acceleration.
When set to one, the PHY will
use the enhancements specified in clause 7.10 of 1394a specifica-
tion. PHY behavior is unspecified if the value of Enab_accel is
changed while a bus request is pending.
Enable multispeed packet concatenation. When set to one, the link
will signal the speed of all packets to the PHY.
Selects which of eight possible PHY register pages are accessible
through the window at PHY register addresses 1000
2
through
1111
2
, inclusive.
If the page selected by Page_select presents per-port information,
this field selects which port’s registers are accessible through the
window at PHY register addresses 1000
2
through 1111
2
, inclusive.
Ports are numbered monotonically starting at zero, p0.
Enab_multi
1
rw
0
Page_select
3
rw
000
Port_select
4
rw
000
Address
Contents
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
1000
2
AStat
BStat
Child
Connected
XXXXX XXXXX
Bias
Disabled
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
1001
2
Negotiated_speed
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
Int_enable
Fault
1010
2
1011
2
1100
2
1101
2
1110
2
1111
2
REQUIRED
XXXXX
RESERVED
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| FW80200M600 | Microprocessor |
| FW80200M733 | Microprocessor |
| FW802 | Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| FW802A | Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| FW801A | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device |
| FW801A-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device |
| FW801BF | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY 1394a-2000 One-Cable Transceiver/Arbiter Device |
| FW801BF-09-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY 1394a-2000 One-Cable Transceiver/Arbiter Device |
| FW802 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
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