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參數(shù)資料
| 型號： | FT232BL-REEL |
| 廠商： | FTDI, Future Technology Devices International Ltd |
| 文件頁數(shù)： | 4/34頁 |
| 文件大小： | 0K |
| 描述： | IC USB FS SERIAL UART 32-LQFP |
| 產(chǎn)品培訓模塊： | USB Introduction |
| 標準包裝： | 1 |
| 系列： | USBmadeEZ-UART |
| 通道數(shù)： | 1，UART |
| FIFO's： | 256 字節(jié) |
| 規(guī)程： | RS232，RS422，RS485 |
| 電源電壓： | 4.35V ~ 5.25V |
| 帶自動流量控制功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應商設備封裝： | 32-LQFP |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 634 (CN2011-ZH PDF) |
| 其它名稱： | 768-1009-6 |
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Copyright 2011 Future Technology Devices International Limited
12
Document No.: FT_000329
FT232BL
/BQ USB UART IC Datasheet Version 2.2
Clearance No.: FTDI#
171
4.2 Functional Block Descriptions
The following paragraphs detail each function within the FT232B. Please refer to the block diagram shown
in Figure 2.1 .
The 3.3V LDO Regulator generates the 3.3 volt reference voltage for driving the USB transceiver cell
output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator
output pin. It also provides 3.3V power to the RSTOUT# pin. The main function of this block is to power
the USB Transceiver and the Reset Generator Cells rather than to power external logic. However,
external circuitry requiring 3.3V nominal at a current of not greater than 5mA could also draw its power
from the 3V3OUT pin if required.
USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface
to the USB cable. The output drivers provide 3.3 volt level slew rate control signalling, whilst a differential
receiver and two single ended receivers provide USB data in, SEO and USB Reset condition detection.
USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock
and data signals for the Serial Interface Engine (SIE) block.
6MHz Oscillator. The 6MHz Oscillator cell generates a 6MHz reference clock input to the x8 Clock
multiplier from an external 6MHz crystal or ceramic resonator
X8 Clock Multiplier. The x8 Clock Multiplier takes the 6MHz input from the Oscillator cell and generates
a 12MHz reference clock for the SIE, USB Protocol Engine and UART FIFO controller blocks. It also
generates a 48MHz reference clock for the USB DPPL and the Baud Rate Generator blocks.
Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial
and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it
performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also checks the CRC on the USB data
stream.
USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control
endpoint. It handles the low level USB protocol (Chapter 9) requests generated by the USB host
controller and the commands for controlling the functional parameters of the UART.
Dual Port TX Buffer (128 bytes). Data from the USB data out endpoint is stored in the Dual Port TX
buffer and removed from the buffer to the UART transmit register under control of the UART FIFO
controller.
Dual Port RX Buffer (384 bytes). Data from the UART receive register is stored in the Dual Port RX
buffer prior to being removed by the SIE on a USB request for data from the device data in endpoint.
UART FIFO Controller. The UART FIFO controller handles the transfer of data between the Dual FIFO RX
and TX buffers and the UART transmit and receive registers.
UART. The UART performs asynchronous 7/8 bit Parallel to Serial and Serial to Parallel conversion of the
data on the RS232 (RS422 and RS485) interface. Control signals supported by the UART include RTS,
CTS, DTR, DSR, DCD and RI. The UART provides a transmitter enable control signal (TXDEN) to assist
with interfacing to RS485 transceivers. The UART supports RTS/CTS, DTR/DSR and X-On/X-Off
handshaking options. Handshaking, where required, is handled in hardware to ensure fast response
times. The UART also supports the RS232 BREAK setting and detection conditions.
Baud Rate Generator. The Baud Rate Generator provides a x16 clock input to the UART from the
48MHz reference clock and consists of a 14 bit prescaler and 3 register bits which provide fine tuning of
the baud rate (used to divide by a whole number plus a fraction). This determines the Baud Rate of the
UART which is programmable from 183 baud to 3M baud.
RESET Generator. The Reset Generator Cell provides a reliable power-on reset to the device internal
circuitry on power up. RESET# input and RSTOUT# output are provided to allow other devices to reset
the FT232B to reset other devices respectively. During reset, RSTOUT# is driven low, otherwise it drives
out at the 3.3V provided by the onboard regulator. RSTOUT# can be used to control the 1.5k pull-up on
USBDP directly where delayed USB enumeration is required. It can also be used to reset other devices.
RSTOUT# will stay high-impedance for approximately 5ms after VCC has risen above 3.5V AND the
device oscillator is running AND RESET# is high. RESET# should be tied to VCC unless it is a requirement
to reset the device from external logic or an external reset generator IC.
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