參數(shù)資料
型號(hào)： FT2232HQ-TRAY
廠商： Future Technology Devices International Ltd
元件分類： 總線控制器
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
封裝： LEAD FREE, QFN-64
文件頁(yè)數(shù)： 7/63頁(yè)
文件大?。?/td> 1598K
代理商： FT2232HQ-TRAY
Copyright 2010 Future Technology Devices International Limited
15
Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 2.10
Clearance No.: FTDI#77
3.4.5 FT2232H pins used in an MPSSE
The FT2232H channel A and channel B each have a Multi-Protocol Synchronous Serial Engine (MPSSE).
Each MPSSE can be independently configured to a number of industry standard serial interface protocols
such as JTAG, I2C or SPI, or it can be used to implement a proprietary bus protocol. For example, it is
possible to use one of the FT2232Hs channels to connect to an SRAM configurable FPGA such as supplied
by Altera or Xilinx. The FPGA device would normally be un-configured (i.e. have no defined function) at
power-up. Application software on the PC could use the MPSSE to download configuration data to the
FPGA over USB. This data would define the hardware function on power up. The other FT2232H channel
would be available for another function. Alternatively each MPSSE can be used to control a number of
GPIO pins. When configured in this mode, the pins used and the descriptions of the signals are shown
Channel A
Pin No.
Channel B
Pin No.
Name
Type
MPSSE Configuration Description
16
38
TCK/SK
OUTPUT
Clock Signal Output. For example:
JTAG – TCK, Test interface clock
SPI – SK, Serial Clock
17
39
TDI/DO
OUTPUT
Serial Data Output. For example:
JTAG – TDI, Test Data Input
SPI – DO
18
40
TDO/DI
INPUT
Serial Data Input. For example:
JTAG – TDO, Test Data output
SPI – DI, Serial Data Input
19
41
TMS/CS
OUTPUT
Output Signal Select. For example:
JTAG – TMS, Test Mode Select
SPI – CS, Serial Chip Select
21
43
GPIOL0
I/O
General Purpose input/output
22
44
GPIOL1
I/O
General Purpose input/output
23
45
GPIOL2
I/O
General Purpose input/output
24
46
GPIOL3
I/O
General Purpose input/output
26
48
GPIOH0
I/O
General Purpose input/output
27
52
GPIOH1
I/O
General Purpose input/output
28
53
GPIOH2
I/O
General Purpose input/output
29
54
GPIOH3
I/O
General Purpose input/output
30
55
GPIOH4
I/O
General Purpose input/output
32
57
GPIOH5
I/O
General Purpose input/output
33
58
GPIOH6
I/O
General Purpose input/output
34
59
GPIOH7
I/O
General Purpose input/output
Table 3.8 Channel A and Channel B MPSSE Configured Pin Descriptions
For a functional description of this mode, please refer to section 4.6 MPSSE Interface Mode Description.
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