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| 型號： | FT2232HQ-TRAY |
| 廠商： | Future Technology Devices International Ltd |
| 元件分類： | 總線控制器 |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQCC64 |
| 封裝： | LEAD FREE, QFN-64 |
| 文件頁數(shù)： | 10/63頁 |
| 文件大?。?/td> | 1598K |
| 代理商： | FT2232HQ-TRAY |
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Copyright 2010 Future Technology Devices International Limited
18
Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 2.10
Clearance No.: FTDI#77
3.4.8 FT2232H Pins Configured as a Host Bus Emulation Interface
The FT2232H can be used to combine channel A and channel B to be configured as a host bus emulation
interface mode which emulates a standard 8048 or 8051 MCU host.
When configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.11
Pin No.
Name
Type
Fast Serial Interface Configuration Description
24,23,22,21,
19,18,17,16
ADBUS[7:0]
I/O
Multiplexed bidirectional Address/Data bus AD7 to AD0
34,33,32,30,
29,28,27,26
A[15:8]
OUTPUT
Extended Address A15 to A8
38
CS#
OUTPUT
Active low chip select device during Read or Write.
39
ALE
OUTPUT
Positive pulse to latch the address
40
RD#
OUTPUT
Active low read output.
41
WR#
OUTPUT
Active low write output. (Data is setup before WR# goes
low, and is held after WR# goes high)
43
IORDY
INPUT
Extends the time taken to perform a Read or Write
operation if driven low. Pull up to VCORE if not being
used.
44
CLKOUT
OUTPUT
Master clock. Outputs the clock signal being used by the
configured interface.
45
I/O0
I/O
MPSSE mode instructions to set / clear or read the high
byte of data can be used with this pin. Please refer to
Application Note AN_108 for operation of these
instructions.
46
I/O1
I/O
MPSSE mode instructions to set / clear or read the high
byte of data can be used with this pin. In addition this
pin has instructions which will make the controller wait
until it is high, or wait until it is low. This can be used to
connect to an IRQ pin of a peripheral chip. The FT2232H
will wait for the interrupt, and then read the device, and
pass the answer back to the host PC. I/O1 must be held
in input mode if this option is used. Please refer to
Application Note AN_108 for operation of these
instructions.
Table 3.11 Channel A and Channel B Host Bus Emulation Interface Configured Pin Descriptions
For a functional description of this mode, please refer to section 4.7 MCU Host Bus Emulation Mode
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