- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375872 > FPD85310 (National Semiconductor Corporation) Panel Timing Controller PDF資料下載
參數(shù)資料
| 型號： | FPD85310 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Panel Timing Controller |
| 中文描述： | 小組定時控制器 |
| 文件頁數(shù)： | 8/29頁 |
| 文件大小： | 440K |
| 代理商： | FPD85310 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
Functional Description
(Continued)
face or custom gate interfaces can be implemented with the
nine GPOs. Note that GPO [8] must be used for output
blanking control.
Five registers provide the timing definition for each GPO.
The Horizontal Start register defines the output pixel number
for which the GPO output goes active. The Horizontal dura-
tion register determines how many clocks the output will re-
main active during the line. The Vertical Start register defines
at what line # the output becomes active, and the Vertical du-
ration register defines how many lines the output remains
active. Each output has a control register (bit 0) which de-
fines the GPO polarity (active high or low). Another bit in the
control register (bit 1) enables the “toggle” mode. This mode
is useful in REV generation when alternating polarity is re-
quired from line to line. Frame to Frame polarity changes are
made by programming an odd # in the vertical duration reg-
ister when in “toggle” mode.
Two of the General Purpose Outputs have additional capa-
bilities. GPO [8] controls output blanking and must be used
for this purpose. If output blanking is not desired, this register
must be programmed to always be active. White data gen-
eration (all “1” data) at the end of each frame is generated
when D6 register bit 7 is set. When this bit is set, white data
is output after line #768 if GPO [8] is active. GPO [0] is ca-
pable of performing line inversion on the output data. Bits
[5:3] of the Output Format Control register provides control
for this function.
See APPENDIX A: GPO Programming Examples
SERIAL EEPROM INTERFACE
The Serial EEPROM Interface controls the FPD85310 initial-
ization. If the EEPROM is not present (EESD and EESC are
pulled high), or if EEPROM address 80H is not “00”, the in-
ternal default values are used to initialize all programmable
functions of the FPD85310.
At power-up, the FPD85310 configures the internal program-
mable registers with data from the EEPROM. After the
FPD85310 is initialized, the EEPROM can be accessed by
the system in which display configuration and manufacturing
information can be obtained. The EEPROM can be pro-
grammed “in system” providing quick evaluation of different
display timing.
External access to the EEPROM must be preceded by ap-
plying a “1” to pin TEST [2] in order to interrupt the
FPD85310 download.
The FPD85310 initialization data begins at EEPROM ad-
dress 80H. The first 128 bytes (0-7F) are reserved for dis-
play identification data.
A power-up delay can be programmed using bits [6:5] of the
Input Format Control Register. This delays outputting (driv-
ing) of the data and control for up to 5 frame times after re-
set. The TEST [2] pin must be low for a power-up delay to
occur.
VERTICAL/HORIZONTAL REFERENCE GENERATOR
AND FAILURE DETECTION
This block provides Vertical and Horizontal Reference points
for the Timing Control Function. VSYNC, HSYNC and ENAB
along with programmable control from the input control reg-
ister bits 0 and 1 (FIX HORIZONTAL and FIX VERTICAL)
are used to determine when the video from the host is valid.
Three input modes are supported. See Table 1
Fixed Vertical, Fixed Horizontal
The horizontal timing is fixed and determined by the Horizon-
tal Backporch register. The vertical timing is also fixed and
determined by the Vertical Backporch register. ENAB is ig-
nored and is not necessary.
Fixed Vertical, ENAB Controlled Horizontal
The horizontal timing is controlled by the ENAB timing. The
vertical timing is fixed and determined by the Vertical Back-
porch register.
ENAB Only
In ENAB Only timing, VSYNC and HSYNC are ignored. All
timing is derived from the ENAB signal.
Failure Detection
The FPD85310 detects the loss of (necessary) control from
the system. VSYNC, HSYNC, ENAB, and CLK are moni-
tored for failure conditions. Failure condition is detected
whenever the input clock stops or when control necessary
for the operational mode is inactive. Failure conditions result
in outputting a default video stream to the panel. Depending
on the mode, loss of CLK, ENAB, HSYNC and/or VSYNC
will result in fail condition output timing. The FPD85310 has
an internal oscillator used for input clock failure detection. If
the input clock quits toggling, the internal oscillator gener-
ates the control timing to the column drivers and row drivers.
The internal ring oscillator is disabled when a “1” is applied to
the TEST [3] pin. This will, of course, disable the clock failure
detection capability of the FPD85310. Further description of
the failure detection modes is given in Table 4
www.national.com
8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FPD87208AXAVS | +2.5V Low EMI, Low Dynamic Power XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling RSDS⑩ Outputs |
| FPD87208 | +2.5V Low EMI, Low Dynamic Power XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling RSDS⑩ Outputs |
| FPD87310 | Universal Interface XGA Panel Timing Controller with RSDS⑩ (Reduced Swing Differential Signaling) and FPD-Link |
| FPD87346 | Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS⑩) Outputs |
| FPD87346VS | Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS⑩) Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FPD85310VJD | 功能描述:IC CTRLR PANEL TIMING 100-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| FPD87208 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:+2.5V Low EMI, Low Dynamic Power XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling RSDS⑩ Outputs |
| FPD87208AXAVS | 制造商:Rochester Electronics LLC 功能描述:2.5V XGA/WXGA TIMING CONTROLER - Bulk |
| FPD87310 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Universal Interface XGA Panel Timing Controller with RSDS⑩ (Reduced Swing Differential Signaling) and FPD-Link |
| FPD87310VHB | 功能描述:IC CTRLR PANEL TIMING 80-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。