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參數(shù)資料
| 型號： | FPD85310 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Panel Timing Controller |
| 中文描述： | 小組定時控制器 |
| 文件頁數(shù)： | 11/29頁 |
| 文件大小： | 440K |
| 代理商： | FPD85310 |
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Functional Description
(Continued)
TABLE 2. FPD85310 Programmable Register Definition
(Continued)
Control
Registers
Output
Enable/Polarity
Control
EEPROM
Address
DB
The control registers provide mode setting information to the input and output interfaces.
[0]
[1]
[2]
[3]
[4]
[5]
[7:6]
OCLK Enable (1-On, 0-TRI-STATE)
OCLK Polarity (1-Per Datasheet, 0-Inverted)
ECLK Enable (1-On, 0-TRI-STATE)
ECLK Polarity (1-Per Datasheet, 0-Inverted)
ORGB/OSP/OPOL Enable (1-On, 0-TRI-STATE)
ERGB/ESP/EPOL Enable (1-On, 0-TRI-STATE)
OSP/ESP Control
[7,6] Output
0,0 Lowest Drive
0,1 ..
1,0 ..
1,1 Highest Drive
OCLK Control
ECLK Control
ORGB/OPOL Control
ERGB/EPOL Control
[A,B]
Output
0,0
Lowest Drive
0,1
..
1,0
..
1,1
Highest Drive
= # Data/CD
This number defines how many contiguous pixels are output on the odd and even data
channels for the single port CD interface. CD sizes of up to 128 pixel (384 channel) are
supported. A minimum value of 20H must be programmed regardless of CD interface
used.
Fix Vertical
“0” = Vertical position dependent on first ENAB from VSYNC
“1” = Vertical position dependent on Vertical Backporch Register
Fix Horizontal
“0” = Horizontal position dependent on ENAB
“1” = Horizontal position dependent on Horizontal Backporch Register
*See Table 1 for valid mode combinations.
Enab detection
“0” = Enab detection off
“1” = Enab detection on (detects if Enab is toggling)
Auto Mode switching when Enab detection = “1”
Fix
Vertical
Horizontal
Toggling
0
0
Yes
ENAB ONLY
0
0
No
FV/FH
1
0
Yes
FV/ENAB HORIZ
1
0
No
FV/FH
1
1
X
FV/FH
Note: Input sync. need to be proceeded before RSTZ goes “high” to determine the “Operating
Mode”
Output Drive
Control
D4
[1:0]
[3:2]
[5:4]
[7:6]
CD Size
D5
[7:0]
Input Format
Control
D6
[0]
[1]
[2]
Fix
Enab
Operating Mode
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