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參數(shù)資料
| 型號： | FPD33684A |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Low Power, Low EMI, TFT-LCD Column Driver with RSDS⑩ Inputs, 64 Grayshades, and 384 Outputs for XGA/SXGA Applications |
| 中文描述： | 低功耗，低EMI，TFT - LCD的柱與⑩輸入?yún)^(qū)特別職務(wù)隊(duì)，64 Grayshades，和384的XGA輸出驅(qū)動器/ SXGA應(yīng)用 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 233K |
| 代理商： | FPD33684A |
AC Electrical Characteristics
Digital AC Characteristics
Symbol
PW
CLK
PW
CLK(L)
PW
CLK(H)
t
setup1
t
hold1
t
setup2
t
hold2
t
PLH1
PW
DIO
PW
CLK1
t
LDT
t
DENSU
tPOL–CLK1
Parameter
Conditions
Min
11.7
5
5
2
0
2
4
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
T
CLK
Clock Period
Low Clock Pulse Width
High Clock Pulse Width
RSDS Data Setup Time
RSDS Data Hold Time
ENIOx Setup Time
ENIOx Hold Time
Start Pulse Fall Delay
ENIOx Pulse Width
LOAD Pulse Width
Last Clock to LOAD Delay
LOAD to First ENIO Setup
POL–CLK1 Time
C
LINE
= 15 pF
8
2
1
5 T
CLK
5
2
14
5μs
T
CLK
T
CLK
ns
Analog AC Characteristics
Supplies: V
SS1
= V
SS2
= 0.0V, V
DD1
= 3.3V, V
DD2
= +9.5V, V
HBIAS
= 11.0V.
Symbol
Parameter
t
settle 90%
Output Settling Time to 90% of
Final Value
t
6-bit accy
Output Settling Time to 6-bit
accuracy
t
RP 90%
Repair Line Output Settling Time
to 90% of Final Value
t
RP 6-bit accy
Repair Line Output Settling Time
to 6-bit accuracy
Conditions
Min
Typ
Max
Units
Figure 2
(Note 12)
6
μs
Figure 2
(Note 12)
10
μs
C
LOAD
= 150 pF,
(Note 12)
C
LOAD
= 150 pF,
(Note 12)
6
μs
10
μs
Note 12:
Charge Share Time = 800ns, V
GMA1
= 10.3V, V
GMA10
= 0.2V, V
GMA5
= 5.45V, V
GMA6
= 5.05V.
DS200113-11
FIGURE 2. Test Circuit for Output Settling Time Measurements
F
www.national.com
4
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