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參數(shù)資料
| 型號： | FM8P51P |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | EPROM/ROM-Based 8-Bit Microcontroller |
| 中文描述： | 存儲器/基于ROM的8位微控制器 |
| 文件頁數(shù)： | 37/60頁 |
| 文件大小： | 369K |
| 代理商： | FM8P51P |
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FM8P51
Rev1.2 Mar 15, 2005
P.37/FM8P51
FEELING
TECHNOLOGY
2.10 Data Comparator
The data comparator can compare two different data in compared data register (CMPDX, CMPDY), and output the
number of different/error bits between CMPDX and CMPDY into CMPF3:CMPF0 bits (CMPSTAT<3:0>).
The data comparator will auto-compare the data of CMPDX to the data of CMPDY whenever any one of (CMPDX,
CMPDY) is changed.
If user write 00h to CMPDX, and write one 8-bit data to CMPDY, then CMPF3:CMPF0 means the number of “1” of
the 8-bit data. Similarly, if user write FFh to CMPDX, and write one 8-bit data to CMPDY, then CMPF3:CMPF0
means the number of “0” of the 8-bit data.
FIGURE 2.15: The Block Diagram of Data Comparator
2.11 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction.
When SLEEP instruction is executed, the
PD
bit (STATUS<3>) is cleared, the TObit is set,
the watchdog timer will
be cleared and keeps running, and the oscillator driver is turned off.
All I/O pins maintain the status they had before the SLEEP instruction was executed.
2.11.1 Wake-up from SLEEP Mode
The device can wake-up from SLEEP mode through one of the following events:
1. RSTB reset.
2. WDT time-out reset (if enabled).
3. Input change wake-up.
External RSTB reset and WDT time-out reset will cause a device reset. The
PD
and TObits can be used to
determine the cause of device reset. The
PD
bit is set on power-up and is cleared when SLEEP instruction is
executed. The TObit is cleared if a WDT time-out occurred.
Any one of the wake-up pins is set to “0”, the device will wake-up and continue execution at the instruction after the
SLEEP instruction. In this case, before entering SLEEP mode, the wake-up function of trigger sources (IOB0~IOB7,
IOC4~IOC5, and IOE0~IOE1) should be selected (e.g. input pin) and enabled (e.g. pull-high, wake-up control (
/WUE bit, PCON<0>)).
The system wake-up delay time is 18ms plus 128 oscillator cycle time.
Data bus
Comparator x8
CMPDX
CMPDY
CMPF3:CMPF0
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