參數(shù)資料
型號(hào)： FM8P51P
廠商： Electronic Theatre Controls, Inc.
英文描述： EPROM/ROM-Based 8-Bit Microcontroller
中文描述： 存儲(chǔ)器/基于ROM的8位微控制器
文件頁(yè)數(shù)： 12/60頁(yè)
文件大?。?/td> 369K
代理商： FM8P51P
FM8P51
Rev1.2 Mar 15, 2005
P.12/FM8P51
FEELING
TECHNOLOGY
2.1.5 FSR (Indirect Data Memory Address Pointer)
Address
Name
04h (r/w)
FSR
Bit5:Bit0
: Select registers address in the indirect addressing mode. See 2.1.1 for detail description.
RP1:RP0
: These bits are used to switching the bank of four data memory banks. See 2.1.1 for detail description.
2.1.6 PORTA, PORTB, PORTC, PORTD & PORTE (Port Data Registers)
Address
Name
B7
B6
B5
05h (r/w)
PORTA
IOA7
IOA6
IOA5
06h (r/w)
PORTB
IOB7
IOB6
IOB5
07h (r/w)
PORTC
IOC7
IOC6
IOC5
08h (r/w)
PORTD
IOD7
IOD6
IOD5
09h (r/w)
PORTE
IOE7
IOE6
IOE5
Reading the port (PORTA, PORTB, PORTC, PORTD, PORTE register) reads the status of the pins independent of
the pin’s input/output modes. Writing to these ports will write to the port data latch.
2.1.7 SPIRCB (SPI Receive Buffer Register) (Bank 0)
Address
Name
B7
B6
B5
0Ah (r/w)
SPIRCB
RC7
RC6
RC5
RC7:RC0
: SPI receives data buffer. Once the 8-bits data have been received, the data in SPI shift register (SPISR)
will be moved to the SPIRCB register.
The data must be read out before the next 8-bits data reception is completed if needed.
The RCBF flag is set when the data in SPISR is moved to the SPIRCB register, and cleared as the
SPIRCB register reads.
2.1.8 SPITXB (SPI Transmit Buffer Register) (Bank 0)
Address
Name
B7
B6
B5
0Bh (r/w)
SPITXB
TX7
TX6
TX5
TX7:TX0
: SPI transmits data buffer. Once the first valid clock pulse appear on SCK pin, the data in SPITXB will be
loaded into SPISR and start to shift in/out.
The new data must be written to SPITXB before the 8-bits data transmission is completed if
needed.
The TXBF flag is set when the data in SPITXB is moved to the SPISR register, and cleared as the
SPITXB register writes.
2.1.9 SPISTAT (SPI Status Register) (Bank 0)
Address
Name
B7
B6
B5
0Ch (r/w)
SPISTAT
-
TXBFIF
TXBF
RCBF
: SPI receive buffer full flag. Set when the data in SPISR is moved to the SPIRCB register, reset by software
or by reading SPIRCB register.
= 1, Receive complete, SPIRCB is full.
= 0, Receive not complete, SPIRCB is empty.
B7
RP1
B6
RP0
B5
B4
Indirect data memory address pointer
B3
B2
B1
B0
B4
IOA4
IOB4
IOC4
IOD4
IOE4
B3
IOA3
IOB3
IOC3
IOD3
IOE3
B2
IOA2
IOB2
IOC2
IOD2
IOE2
B1
IOA1
IOB1
IOC1
IOD1
IOE1
B0
IOA0
IOB0
IOC0
IOD0
IOE0
B4
RC4
B3
RC3
B2
RC2
B1
RC1
B0
RC0
B4
TX4
B3
TX3
B2
TX2
B1
TX1
B0
TX0
B4
B3
B2
B1
B0
TM1IF
SDOOD
SCKOD
RCBFIF
RCBF
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