參數(shù)資料
型號(hào)： FIN24A
廠商： Fairchild Semiconductor Corporation
英文描述： Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)
中文描述： 低電壓24位雙向串行器/有多個(gè)頻率范圍串器（初步）
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 1758K
代理商： FIN24A
Preliminary
www.fairchildsemi.com
12
F
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Note 5:
Skew is measured from either the rising or falling edge of the clock (CKSO) relative to the center of the data bit (DSO). Both outputs should have
identical load conditions for this to be valid.
Note 6:
This jitter specification is based on the assumption that PLL has a REF Clock with cycle-to-cycle input jitter less than 2ns.
Note 7:
The power-downtime is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the state of the S1/S2 mode pins. The
specific number of clock cycles required for the PLL to be disabled will vary dependent upon the operating mode of the device.
Note 8:
Signals are transmitted from the serializer source synchronously. Note that in some cases data is transmitted when the clock remains at a high state.
Skew should only be measured when data and clock are transitioning at the same time. Total measured input skew would be a combination of output skew
from the serializer, load variations and ISI and jitter effects.
Note 9:
Rising edge of CKP will appear approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP will occur approximately 6 bit
times after a data transition. Variation with respect to the CKP signal is due to internal propagation delays of the device. Note that if CKREF is not equal to
STROBE for the serializer the CKP signal will not maintain a 50% Duty Cycle. The low time of CKP will remain 13 bit times.
Symbol
Serializer Electrical Characteristics
t
TCP
CKREF Clock Period
(2 MHz - 30 MHz)
Parameter
Test Conditions
Min
Typ
Max
Units
See Figure 17
S2
0
S1
1
200
T
500
ns
CKREF
STROBE
S2
1
S1
0
66.0
200
S2
1
S1
1
33.0
100
f
REF
CKREF Frequency Relative
to Strobe Frequency
CKREF
does not equal
STROBE
S2
0
S2
1
S2
1
S1
1
S1
0
S1
1
1.1 *
f
ST
5.0
15.0
30.0
MHz
t
CPWH
t
CPWL
t
CLKT
t
SPWH
t
SPWL
f
MAX
CKREF Clock High Time
CKREF Clock Low Time
LVCMOS Input Transition Time
TBD
TBD
0.5
0.5
TBD
TBD
TBD
T
T
ns
See Figure 17
STROBE Pulse Width HIGH
STROBE Pulse Width LOW
Maximum Serial Data Rate
See Figure 17
See Figure 17
CKREF x 26
5.0
5.0
52.0
ns
ns
S2
0
S1
1
130
Mb/s
S2
1
S2
1
S1
0
S1
1
130
260
390
780
Serializer AC Electrical Characteristics
t
TLH
Differential Output Rise Time (20% to 80%)
t
THL
Differential Output Fall Time (80% to 20%)
t
STC
DP[n] Setup to STROBE
t
HTC
DP[n] Hold to STROBE
t
TCCD
Transmitter Clock Input to
Clock Output Delay
See Figure 14
0.6
0.6
0.9
0.9
ns
ns
ns
DIRI
1
2.5
See Figure 16 (f
10 MHz)
See Figure 20, DIRI
1,
CKREF
STROBE
0
ns
TBD
TBD
TBD
ns
t
SPOS
CKSO Position Relative to DS
See Figure 23, (Note 5)
CKREF Serialization Mode
See Figure 23, (Note 5)
TBD
TBD
TBD
TBD
TBD
TBD
No CKREF Serialization Mode
PLL AC Electrical Characteristics Specifications
t
JCC
CKSO Clock Out Jitter (Cycle-to-Cycle)
t
TPLLS0
Serializer Phase Lock Loop Stabilization
Time
t
TPLLD0
PLL Disable Time Loss of Clock
t
TPLLD1
PLL Power-Down Time
Deserializer AC Electrical Characteristics
t
S_DS
Serial Port Setup Time, DS-to-CKSI
t
H_DS
Serial Port Hold Time, DS-to-CKS
t
RCOP
Deserializer Clock Output (CKP OUT) Period Figure 18
t
RCOL
CKP OUT Low Time
t
RCOH
CKP OUT High Time
(Note 6)
TBD
ns
See Figure 19
1000
Cycles
See Figure 24, (Note 7)
3.0
10.0
us
See Figure 25
20.0
ns
Figure 22, (Note 8)
500
ps
Figure 22, (Note 8)
500
33.0
13a-3
ps
ns
ns
T
500
13a 3
Figure 18 (Rising Edge Strobe)
Serializer Source STROBE
CKREF
Where a
(1/f)/26 (Note 9)
Figure 18 (Rising Edge Strobe)
13a-3
13a 3
ns
t
PDV
Data Valid to CKP LOW
6a-3
6a
6a 3
ns
Where a
(1/f)/26 (Note 9)
C
L
8 pF
Figure 15
t
ROLH
t
ROHL
Output Rise Time (20% to 80%)
Output Fall time (80% to 20%)
2.5
2.5
5.0
5.0
ns
ns
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