參數資料
型號： FIN24A
廠商： Fairchild Semiconductor Corporation
英文描述： Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)
中文描述： 低電壓24位雙向串行器/有多個頻率范圍串器（初步）
文件頁數： 10/20頁
文件大?。?/td> 1758K
代理商： FIN24A
Preliminary
www.fairchildsemi.com
10
F
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2:
Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside datasheet specifi-
cations.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Supply Voltage (V
DD
)
ALL Input/Output Voltage
LVDS Output Short Circuit Duration
Storage Temperature Range (T
STG
)
Maximum Junction Temperature (T
J
)
Lead Temperature (T
L
)
(Soldering, 4 seconds)
ESD Rating
Human Body Model, 1.5K
:
, 100pF
Machine Model, 0
:
, 200pF
0.5V to 4.6V
0.5V to 4.6V
Continuous
65
q
C to 150
q
C
150
q
C
260
q
C
!
2kV
!
200V
Supply Voltage (V
DDA
, V
DDS
)
Supply Voltage (V
DDP
)
Operating Temperature (T
A
) (Note 2)
Supply Noise Voltage (V
DDA-PP
)
2.775V
r
5.0%V
1.65V to 3.6V
10
q
C to 70
q
C
100 mV
P-P
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
(Note 3)
LVCMOS I/O
V
IH
V
IL
V
OH
Input High Voltage
Input Low Voltage
0.65 x V
DDP
GND
V
DDP
0.35 x V
DDP
V
Output High Voltage
I
OH
2.0 mA
V
DDP
3.3
r
0.3
V
DDP
2.5
r
0.2
V
DDP
1.8
r
0.15
V
DDP
3.3
r
0.3
V
DDP
2.5
r
0.2
V
DDP
1.8
r
0.15
0.75 x V
DDP
V
V
OL
Output Low Voltage
V
I
OL
2.0 mA
0.25 x V
DDP
I
IN
I
I(Hold)
Input Current
Minimum Bushold Currents
V
IN
0V to 3.6V
V
DDP
3.0, V
IN
1.95 or 1.05
V
DDP
2.3, V
IN
1.495 or 0.805
V
DDP
1.65, V
IN
1.07 or 0.58
V
DDP
3.6, V
IN
2.34 or 1.26
V
DDP
2.7, V
IN
1.76 or 0.945
V
DDP
1.95, V
IN
1.268 or 0.682
V
DDP
0V, V
DDS
0, V
DDA
0
ALL LVCMOS Inputs/ Outputs 0V to 3.6V
5.0
5.0
P
A
r
35.0
r
25.0
uA
r
10.0
r
200
r
150
I
I(OD)
Minimum Required Bushold
Overdrive Current
uA
r
75.0
I
OFF
Input/Output Power-Off
Leakage Current
r
5.0
P
A
DIFFERENTIAL I/O
V
OD
'
V
OD
Output Differential Voltage
V
OD
Magnitude Change from
Differential LOW-to-HIGH
Offset Voltage
Offset Magnitude Change from
R
L
100
:
, See Figure
150
225
350
mV
R
L
100
:
, See Figure
15.0
mV
V
OS
'
V
OS
R
L
100
:
, See Figure
V
DD
2.775
r
5%
925
mV
15.0
mV
Differential LOW-to-HIGH
Short Circuit Output Current
(Note 4)
I
OS
V
OUT
0V
Driver Enabled
Driver Disabled
2.5
5.0
r
5.0
mA
P
A
I
OZ
V
TH
V
TL
V
ICM
R
TRM0
Disabled Output Leakage Current DP
0V to V
DDP
, DIRI
V
DDP
Differential Input Threshold HIGH
Differential Input Threshold LOW
r
1.0
r
10.0
P
A
mV
mV
See Figure 12 and Table 2
See Figure 12 and Table 2
100
100
Input Common Mode Range
CKSI Internal Receiver
Termination Resistor
V
DD
2.775
r
5%
V
ID
225 mV, V
IC
925 mV, DIRI
0
|CKSI CKSI |
V
ID
V
ID
225 mV, V
IC
925 mV, DIRI
0
|DS DSI |
V
ID
300
925
1550
mV
80.0
100
120
:
DS I/O Termination Resistor
80.0
100
120
相關PDF資料
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