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參數(shù)資料
| 型號(hào)： | FIN212ACMLX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SERIAL/DESERIAL 12BIT 32MLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SerDes™ |
| 功能： | 串行器/解串器 |
| 數(shù)據(jù)速率： | 560Mbps |
| 輸入類型： | LVCMOS |
| 輸出類型： | LVCMOS |
| 輸入數(shù)： | 12 |
| 輸出數(shù)： | 12 |
| 電源電壓： | 1.65 V ~ 3.6 V |
| 工作溫度： | -30°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-MLP |
| 供應(yīng)商設(shè)備封裝： | 32-MLP（5x5） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1216 (CN2011-ZH PDF) |
| 其它名稱： | FIN212ACMLXDKR |
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN212AC Rev. 1.1.1
2
S
erDe
s
FIN212
AC
—
12
-Bit
Se
rial
izer
/
De
seriali
zer
Suppo
rti
ng
Ca
meras
and
Small
Displays
FIN212AC (Serializer DIRI=1) Pin Descriptions
Pin Name
Description
DIRI
Control to determine serializer or deserializer configuration.
0
Deserializer
1
Serializer
CTL_ADJ
Adjusts CTL drive to compensate for environmental conditions
and length.
0
Low drive (low power)
1
High drive (high power)
S0
Configure frequency range for the PLL.
See Table 1 Serializer (DIRI=1) Control Pin.
S1
Configure frequency range for the PLL.
See Table 1 Serializer (DIRI=1) Control Pin.
PLL0
Divide or adjust the serial frequency.
See Table 1 Serializer (DIRI=1) Control Pin.
PLL1
Divide or adjust the serial frequency.
See Table 1 Serializer (DIRI=1) Control Pin.
CKREF
LV-CMOS clock input and PLL reference.
STROBE
LV-CMOS strobe input for latching data (DP [1:12]) into the serializer on the rising edge.
DP[1:12]
LV-CMOS parallel data input. (GND input if not used)
CKSO+
CKSO-
CTL Differential serializer output bit clock.
CKSO+: Positive signal; CKSO-: Negative signal.
DSO+
DSO-
CTL Differential serial output data signals.
DSO+: Positive signal; DSO-: Negative signal.
CKSI+
CKSI-
CTL Differential deserializer input bit clock.
CKSI+: Positive signal; CKSI-: Negative signal.
No connect unless in “clock pass-through” mode.
CKP
LV-CMOS word clock output or Pixel clock output.
No connect unless in “clock pass-through” mode.
/DIRO
LV-CMOS output, Inversion of DIRI in normal operation. Can be used to drive the DIRI signal
of the deserializer where the interface needs to be turned around.
No connect if not used.
VDDP
Power supply for parallel I/O. (All VDDP pins must be connected to VDDP)
VDDS
Power supply for serial I/O.
VDDA
Power supply for core.
GND
All GND pins must be connected to ground. BGA: all GND pads. MLP: Pin 29 & GND PAD must be grounded.
N/C
No connect. (Do not connect to GND or VDD)
Note:
1.
0=GND; 1=VDDP
FIN212AC (Serializer DIRI=1) Pin Configurations
GND
DP[2]
CKREF
DP[5]
DP[1]
STROBE
DP[3]
VDDP
GND
PLL1
1
A
3
4
5
6
2
B
C
D
E
F
G
DP[4]
CTL_ADJ
DP[6]
/DIRO
CKP
CKSO+
CKSO-
DP[7]
DSO-
DSO+
DP[8]
DP[9]
VDDS
CKSI+
CKSI-
DP[10]
VDDA
DIRI
PLL0
S1
S0
GND
DP[11]
DP[12]
N/C
12
13
14
15
31
30
28
27
26
25
SERIALIZER
GND PAD
DP[4]
CKSO+
CKSO-
DSO+
DSO-
CKSI-
CKSI+
DIRI
VDDS
DP[
3]
DP[
2]
DP[
1]
GND
CT
L_A
DJ
STR
OBE
CKR
EF
/DIRO
PLL1
PLL0
S1
S0
VDD
A
1
DP[5] 2
4
DP[6]
VDDP
3
CKP 5
DP[7] 6
DP[8] 7
DP[9] 8
9
DP[
10
]
32
20
21
19
23
18
16
17
22
24
29
10
DP[
11
]
11
DP[
12
]
42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View)
32-pin MLP, 5 x 5mm, .5mm pitch (Top View)
Figure 2. FIN212AC (Serializer DIRI=1) Pin Assignments (Top View)
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