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參數(shù)資料
| 型號(hào)： | FIN212ACMLX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SERIAL/DESERIAL 12BIT 32MLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SerDes™ |
| 功能： | 串行器/解串器 |
| 數(shù)據(jù)速率： | 560Mbps |
| 輸入類型： | LVCMOS |
| 輸出類型： | LVCMOS |
| 輸入數(shù)： | 12 |
| 輸出數(shù)： | 12 |
| 電源電壓： | 1.65 V ~ 3.6 V |
| 工作溫度： | -30°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-MLP |
| 供應(yīng)商設(shè)備封裝： | 32-MLP（5x5） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1216 (CN2011-ZH PDF) |
| 其它名稱： | FIN212ACMLXDKR |
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN212AC Rev. 1.1.1
5
S
erDe
s
FIN212
AC
—
12
-Bit
Se
rial
izer
/
De
seriali
zer
Suppo
rti
ng
Ca
meras
and
Small
Displays
Pulse Width Calculations
CKP Pulse Width Low Time=(PLL Multiplier * Pwidth Multiplier) / (CKREF*14)
(1)
Example: CKREF=26MHz
; PLL Multiplier=2; Pwidth Multiplier=13
CKP Pulse width=(2 * 13) / (26MHz * 14)=71.4ns
(2)
Power-Down States
When both S1 and S0 signals are 0, regardless of the state of the DIRI signal, the FIN212AC resets and powers down. The
power-down mode shuts down all internal analog circuitry, disables the serial input and output of the device, and resets all
internal digital logic. Table 3: Power-Down indicates the state of the input states and output buffers in Power-Down mode.
Signal Pins
DIRI=1 (Serializer)
DIRI=0 (Deserializer)
DP[12:1]
Inputs Disabled
High-Z
CKP
HIGH
High-Z
STROBE
Input Disabled
CKREF
Input Disabled
/DIRO
0
1
Table 3: Power-Down
Clock Pass-Through Mode
Clock pass-through mode allows a harmonic rich clock source to be sent to the serializer in a CTL format to reduce the overall
harmonic content of the phone, and can reduce the need for EMI filters. The Master Clock Pass through mode performs a
translation to the clock in the CTL link, and does not serialize this signal.
The following describes how to enable this
functionality for an image sensor (See Figure 6).
Deserializer Configuration (DIRI=0)
1.
Connect CKREF(BGA pin A6) to GROUND
2.
Connect master clock to STROBE (BGA pin B5)
Serializer Configuration (DIRI=1)
1.
CKSI passes master clock to CKP output (BGA pin C1)
CKREF and STROBE Signals
Please note that there is a setup and hold time between STROBE and data that must be met as seen on the electrical
characteristics section. The relationship between CKREF and STROBE can be synchronous or asynchronous depending on
what is available in the system. It is suggested that if the signals are synchronous and in normal operation that CKREF is tied
to STROBE as close to the chip as possible. If you are running an asynchronous or spread spectrum setup, please be aware
this may result on cycle jitter on the CKP signal. They cycle jitter does not effect the output data and clock relationship, the
display or end application should continue to work as normal.
PLL Note
Please note that the PLL ranges can overlap, power consumption can be reduced by selecting the operation in the lower end
of the higher speed PLL range.
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| FIN212FZ WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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