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參數(shù)資料
| 型號： | FIN212ACMLX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SERIAL/DESERIAL 12BIT 32MLP |
| 標準包裝： | 1 |
| 系列： | SerDes™ |
| 功能： | 串行器/解串器 |
| 數(shù)據(jù)速率： | 560Mbps |
| 輸入類型： | LVCMOS |
| 輸出類型： | LVCMOS |
| 輸入數(shù)： | 12 |
| 輸出數(shù)： | 12 |
| 電源電壓： | 1.65 V ~ 3.6 V |
| 工作溫度： | -30°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-MLP |
| 供應商設備封裝： | 32-MLP（5x5） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 1216 (CN2011-ZH PDF) |
| 其它名稱： | FIN212ACMLXDKR |
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN212AC Rev. 1.1.1
10
S
erDe
s
FIN212
AC
—
12
-Bit
Se
rial
izer
/
De
seriali
zer
Suppo
rti
ng
Ca
meras
and
Small
Displays
AC Electrical Characteristics
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Serializer Input Operating Conditions
fCKREF
CKREF Clock Frequency
(5MHz - >40MHz);
fCKREF=fSTRB
S1=0, S0=1
18
40
MHz
S1=1, S0=0
5
14
S1=1, S0=1
10
28
fSTRB
Strobe Frequency Relative to
CKREF Frequency
fCKREF ≠ fSTRB
PLL1=0, PLL0=0
100
% of
fCKREF
PLL1=0, PLL0=1
100
PLL1=1, PLL0=0
50
PLL1=1, PLL0=1
33
1/
3
tCPWH
CKREF DC
T=1/fCKREF
0.2
0.5
0.8
T
tCPWL
CKREF DC
T=1/fCKREF
0.2
0.5
0.8
T
tCLKT
LVCMOS Input Transition Time
10-90%
20
ns
tSPWH/L
STROBE Pulse Width HIGH/LOW
T=1/fCKREF
T x
4/
14
T x
10/
14
ns
tSTC
DP(n) Setup to STROBE
(DIRI=1, f=5MHz)
S T R O B E
D P [1 : 1 2]
D ata
t
S T C
t
H T C
S T R O B E
D P [1 : 1 2]
D ata
Setup Time
Hold Time
2.5
ns
tHTC
DP(n) Hold to STROBE
(DIRI=1, f=5MHz)
2.0
ns
Serializer AC Electrical Characteristics
tTCCD
Transmitter Clock Input to Clock
Output Delay
t
TCCD
VDD/2
STROBE
CKS-
CKS+
V
DIFF
=0
Note: STROBE=CKREF
CKP
t
RCCD
VDD/2
DIRI=1, fCKREF=fSTRB
21a+1.5
23a+6.5
ns
Phase Lock Loop (PLL) AC Electrical Characteristics
tTPLLS0
Serializer PLL Stabilization Time
CKREF toggling and stable
200
600
μs
tTPLLD0
PLL Disable Time Loss of Clock
30.0
μs
tTPLLD1
PLL Power-Down Time
20.0
ns
Deserializer AC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
tRCOL
C K P
DP [1:12]
Data
Data Valid
t
PDV
CKP
t
RCOH
t
RCOL
t
RCOP
75%
25%
50%
Setup: DIRI= 0, CKSI and DS are valid signals.
PWS1
PWS0
ns
fSTRB=fCKREF
0
7a-3
7a+3
fSTRB=fCKREF
0
1
7a-3
7a+3
fSTRB=.5x fCKREF
1
0
13a-3
13a+3
fSTRB=.5x fCKREF
1
17a-3
17a+3
tPDV
Data Valid to CKP HIGH (Rising Edge
STROBE), CL=5pF
8a-3
8a+3
ns
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