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參數(shù)資料
| 型號： | FEDL7204-001DIGEST-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 元件分類： | Codec |
| 英文描述： | The ML7204-001 is a speech CODEC for VoIP. |
| 中文描述： | 在ML7204 - 001是一種VoIP語音編解碼器。 |
| 文件頁數(shù)： | 24/42頁 |
| 文件大?。?/td> | 792K |
| 代理商： | FEDL7204-001DIGEST-01 |
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FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
24/42
INTB/GPIOA[6]
Primary function: INTB
This in an interrupt request output pin.
When the interrupt cause is changed, this pin outputs a “L” level for about 1.0
μ
s. When the interrupt factor is
not changed, “H” is output. The interrupt factor can be checked by reading CR16-CR22. Table 1 lists the
interrupt causes.
The interrupt causes can be masked individually in the internal memory (interrupt cause mask control).
Table 1 Interrupt Causes
CR
BIT
Register name
Rising
edge
Falling
edge
Remarks
B2
FSK receive overrun error notification register
(FDET_OER)
FSK receive framing error notification register
(FDET_FER)
FSK receive data read request notification register
(FDET_RQ)
FSK output data setting completion flag
(FGEN_FLAG)
Timer overflow display register (TMOVF)
DSP status register (DSP_ERR)
TONE1 detector detection status register
(TONE1_DET)
TONE0 detector detection status register
(TONE0_DET)
TGEN1 execution flag display register
(TGEN1_EXFLAG)
TGEN0 execution flag display register
(TGEN0_EXFLAG)
Dial pulse detector detection status register
(DP_DET)
DTMF detector detection status register
(DTMF_DET)
DTMF code display register (DTMF_CODE[3:0])
CH2 transmit error status register (TXERR_CH2)
CH1 transmit error status register (TXERR_CH1)
CH2 transmit request notification register
(FR0_CH2)
CH1 transmit request notification register
(FR0_CH1)
CH2 receive error status register (RXERR_CH2)
CH1 receive error status register (RXERR_CH1)
Receive invalid write error notification register
(RXBW_ERR)
Receive request notification register (FR1)
{
: With INTB interrupt generation function
×
: Without INTB interrupt generation function
Secondary function: GPIOA[6]
When the primary function/secondary function selection register (GPFA[6]) of GPIOA[6] is set to “1”, this pin
functions as a general-purpose I/O port GPIOA[6].
{
×
B1
{
×
CR16
B0
{
×
CR17
B0
×
{
CR18
B0
B7
{
{
×
×
B4
{
{
B3
{
{
B2
{
{
CR19
B1
{
{
B6
{
{
B4
{
{
CR20
B3-B0
B3
B2
{
{
{
{
{
{
B1
{
×
CR21
B0
{
×
B3
B2
{
{
{
{
B1
{
{
CR22
B0
{
×
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