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參數(shù)資料
| 型號(hào)： | FDMF8700 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | MOSFETs |
| 英文描述： | Driver plus FET Multi-chip Module |
| 中文描述： | HALF BRDG BASED MOSFET DRIVER, QCC56 |
| 封裝： | 8 X 8 MM, ROHS COMPLIANT, MO-220WLLD-5, SMD-56 |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大?。?/td> | 563K |
| 代理商： | FDMF8700 |
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www.fairchildsemi.com
FDMF8700 Rev. C3
F
Description of Operation
Circuit Description
The FDMF8700 is a driver plus FET module optimized for
synchronous buck converter topology. A single PWM input
signal is all that is required to properly drive the high-side and
the low-side MOSFETs. Each part is capable of driving speeds
up to 500KHz.
Low-Side Driver
The low-side driver (LDRV) is designed to drive a ground
referenced low R
DS(ON)
N-channel MOSFET. The bias for LDRV
is internally connected between VCIN and CGND. When the
driver is enabled, the driver's output is 180° out of phase with
the PWM input. When the driver is disabled (DISB = 0V), LDRV
is held low.
High-Side Driver
The high-side driver (HDRV) is designed to drive a floating
N-channel MOSFET. The bias voltage for the high-side driver is
developed by a bootstrap supply circuit, consisting of the
internal diode and external bootstrap capacitor (C
BOOT
). During
start-up, VSWH is held at PGND, allowing C
BOOT
to charge to
VCIN through the internal diode. When the PWM input goes
high, HDRV will begin to charge the high-side MOSFET's gate
(Q1). During this transition, charge is removed from C
BOOT
and
delivered to Q1's gate. As Q1 turns on, VSWH rises to V
IN
,
forcing the BOOT pin to V
IN
+V
C(BOOT)
, which provides
sufficient VGS enhancement for Q1. To complete the switching
cycle, Q1 is turned off by pulling HDRV to VSWH. C
BOOT
is then
recharged to VCIN when VSWH falls to PGND. HDRV output is
in phase with the PWM input. When the driver is disabled, the
high-side gate is held low.
Adaptive Gate Drive Circuit
The driver IC embodies an advanced design that ensures
minimum MOSFET dead-time while eliminating potential
shoot-through (cross-conduction) currents. It senses the state of
the MOSFETs and adjusts the gate drive, adaptively, to ensure
they do not conduct simultaneously. Refer to Figure 24 and 25
for the relevant timing waveforms.
To prevent overlap during the low-to-high switching transition
(Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage
at the LDRV pin. When the PWM signal goes HIGH, Q2 will
begin to turn OFF after some propagation delay (t
PDL(LDRV)
).
Once the LDRV pin is discharged below ~1.2V, Q1 begins to
turn ON after adaptive delay t
PDH(HDRV)
.
To preclude overlap during the high-to-low transition (Q1 OFF to
Q2 ON), the adaptive circuitry monitors the voltage at the SW
pin. When the PWM signal goes LOW, Q1 will begin to turn OFF
after some propagation delay (t
PDL(HDRV)
). Once the VSWH pin
falls below ~2.2V, Q2 begins to turn ON after adaptive delay
t
pdh(LDRV)
.
Additionally, V
GS
of Q1 is monitored. When V
GS(Q1)
is
discharged below ~1.2V, a secondary adaptive delay is initiated,
which results in Q2 being driven ON after t
PDH(LDRV),
regardless
of SW state. This function is implemented to ensure C
BOOT
is
recharged each switching cycle, particularly for cases where the
power convertor is sinking current and SW voltage does not fall
below the 2.2V adaptive threshold. Secondary delay t
PDH(HDRV)
is longer than t
PDH(LDRV)
.
DISB
V
IL(DISB)
V
IH(DISB)
t
PDL(DISB)
t
PDH(DISB)
LDRV / HDRV
V
IH(PWM)
PWM
t
PDL(LDRV)
LDRV
Figure 24. Output Disable Timing
t
PDH(HDRV)
1.2V
HDRV-SW
t
PDL(HDRV)
SW
2.2V
t
PDH(LDRV)
V
IL(PWM)
Figure 25. Adaptive Gate Drive Timing
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