參數(shù)資料
型號： FDG6317NZ
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 小信號晶體管
英文描述： Dual 20v N-Channel PowerTrench MOSFET
中文描述： 700 mA, 20 V, 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET
封裝： ROHS COMPLIANT, SC-70, 6 PIN
文件頁數(shù)： 2/5頁
文件大?。?/td> 138K
代理商： FDG6317NZ
FDG6317NZ Rev B (W)
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Test Conditions
Symbol
Parameter
Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain–Source Breakdown
Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage
Gate–Body Leakage
V
GS
= 0 V,
I
D
= 250
μ
A
20
V
BV
DSS
T
J
I
DSS
I
GSS
I
GSS
I
D
= 250
μ
A, Referenced to 25
°
C
13
mV/
°
C
V
DS
= 16 V,
V
GS
=
±
12 V, V
DS
= 0 V
V
GS
=
±
4.5 V,V
DS
= 0 V
V
GS
= 0 V
1
μ
A
μ
A
μ
A
±
10
±
1
On Characteristics
V
GS(th)
V
GS(th)
T
J
R
DS(on)
(Note 2)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
V
DS
= V
GS
,
I
D
= –250
μ
A, Referenced to 25
°
C
I
D
= 250
μ
A
0.6
1.2
–2
1.5
V
mV/
°
C
V
GS
= 4.5 V, I
D
= 0.7 A
V
GS
= 2.5 V, I
D
= 0.6 A
V
GS
= 4.5 V, I
D
= 0.7 A, T
J
=125°C
V
GS
= 4.5 V,
V
DS
= 5 V
V
DS
= 5 V,
I
D
= 0.7 A
300
450
390
400
550
560
m
I
D(on)
g
FS
On–State Drain Current
Forward Transconductance
1
A
S
1.8
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
R
G
Gate Resistance
66.5
19
10
5.8
pF
pF
pF
V
DS
= 10 V,
f = 1.0 MHz
V
GS
= 0 V,
V
GS
= 15 mV, f = 1.0 MHz
Switching Characteristics
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
(Note 2)
5.5
7
7.5
2.5
0.76
0.18
0.20
11
15
15
5
1.1
ns
ns
ns
ns
nC
nC
nC
V
DD
= 10 V,
V
GS
= 4.5 V, R
GEN
= 6
I
D
= 1 A,
V
DS
= 10 V,
V
GS
= 4.5 V
I
D
= 0.7 A,
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
V
SD
Drain–Source Diode Forward
Voltage
t
rr
Diode Reverse Recovery Time
Q
rr
Diode Reverse Recovery Charge
0.25
1.2
A
V
V
GS
= 0 V,
I
S
= 0.25 A
(Note 2)
0.8
8.3
1.2
nS
nC
I
F
= 0.7 A,
d
iF
/d
t
= 100 A/μs
Notes:
1.
R
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
JA
is determined by the user's board design. R
θ
JA
= 415°C/W when mounted on a minimum pad .
2.
Pulse Test: Pulse Width < 300
μ
s, Duty Cycle < 2.0%
3.
The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
F
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