參數(shù)資料
型號: FDG314P
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 小信號晶體管
英文描述: Digital FET, P-Channel
中文描述: 650 mA, 25 V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET
封裝: SC-70, 6 PIN
文件頁數(shù): 1/5頁
文件大?。?/td> 84K
代理商: FDG314P
F
FDG314P Rev.C
FDG314P
Digital FET, P-Channel
July 2000
2000 Fairchild Semiconductor International
Absolute Maximum Ratings
T
A
= 25°C unless otherwise noted
Symbol
Parameter
Ratings
Units
V
DSS
V
GSS
I
D
Drain-Source Voltage
Gate-Source Voltage
Drain Current
-25
±
8
-0.65
-1.8
0.75
0.48
V
V
A
- Continuous
- Pulsed
(Note 1a)
Power Dissipation for Single Operation
(Note 1a)
W
P
D
(Note 1b)
T
J
, T
stg
ESD
Operating and Storage Junction Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf/1500 Ohm)
-55 to +150
°
C
kV
6.0
Thermal Characteristics
R
θ
JA
Thermal Resistance, Junction-to-Ambient
(Note 1b)
260
°
C/W
Package Marking and Ordering Information
Device Marking
.
14
Device
FDG314P
Reel Size
7’’
Tape Width
8mm
Quantity
3000 units
General Description
This P-Channel enhancement mode field effect
transistor is produced using Fairchild Semiconductor’s
proprietary, high cell density, DMOS technology. This
very high density process is tailored to minimize on-
state resistance at low gate drive conditions. This
device is designed especially for battery power
applications such as notebook computers and cellular
phones. This device has excellent on-state resistance
even at gate drive voltages as low as 2.5 volts.
Applications
Power Management
Load switch
Signal switch
Features
-0.65 A, -25 V. R
DS(ON)
= 1.1
@ V
GS
= -4.5 V
R
DS(ON)
= 1.5
@ V
GS
= -2.7 V.
Very low gate drive requirements allowing direct
operation in 3V cirucuits (V
GS(th)
<1.5 V).
Gate-Source Zener for ESD ruggedness
(>6 kV Human Body Model).
Compact industry standard SC70-6 surface mount
package.
SC70-6
D
S
DG
D
D
3
5
6
4
1
2
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