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參數(shù)資料
| 型號(hào)： | FDC6322C |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 小信號(hào)晶體管 |
| 英文描述： | Dual N & P Channel , Digital FET |
| 中文描述： | 220 mA, 25 V, 2 CHANNEL, N AND P-CHANNEL, Si, SMALL SIGNAL, MOSFET |
| 封裝： | SUPERSOT-6 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 96K |
| 代理商： | FDC6322C |
November 1997
FDC6322C
Dual N & P Channel , Digital FET
General Description
Features
Absolute Maximum Ratings
T
A
= 25
o
C unless other wise noted
Symbol
Parameter
N-Channel
P-Channel
Units
V
DSS
, V
CC
Drain-Source Voltage, Power Supply Voltage
25
-25
V
V
GSS
, V
IN
Gate-Source Voltage,
8
-8
V
I
D
, I
O
Drain/Output Current
- Continuous
0.22
-0.46
A
- Pulsed
0.5
-1
P
D
Maximum Power Dissipation
(Note 1a)
0.9
W
(Note 1b)
0.7
T
J
,T
STG
ESD
Operating and Storage Tempature Ranger
-55 to 150
°C
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
6
kV
THERMAL CHARACTERISTICS
R
θ
J A
R
θ
J
C
Thermal Resistance, Junction-to-Ambient
(Note 1a)
140
°C/W
Thermal Resistance, Junction-to-Case
(Note 1)
60
°C/W
FDC6322C.Rev B1
N-Ch 25 V, 0.22 A, R
DS(ON)
= 5
@ V
GS
= 2.7 V.
P-Ch 25 V, -0.46 A, R
DS(ON)
= 1.5
@ V
GS
= -2.7 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits. V
GS(th)
< 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace NPN & PNP digital transistors.
These dual N & P Channel logic level enhancement mode field
effec transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
The device is an improved design especially for low voltage
applications as a replacement for bipolar digital transistors in
load switching applications. Since bias resistors are not
required, this dual digital FET can replace several digital
transistors with difference bias resistors.
Mark: .322
SOT-23
SuperSOT
TM
-8
SOIC-16
SO-8
SOT-223
SuperSOT
TM
-6
1
5
3
2
6
4
1997 Fairchild Semiconductor Corporation
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