參數(shù)資料
型號(hào)： FDB8453LZ
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： JFETs
英文描述： N-Channel PowerTrench㈢ MOSFET
中文描述： 50 A, 40 V, 0.011 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-263AB
封裝： ROHS COMPLIANT, TO-263AB, 3 PIN
文件頁(yè)數(shù)： 2/6頁(yè)
文件大小： 256K
代理商： FDB8453LZ
F
www.fairchildsemi.com
2
2007 Fairchild Semiconductor Corporation
FDB8453LZ Rev.C1
Electrical Characteristics
T
J
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
BV
DSS
T
J
I
DSS
I
GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
D
= 250
μ
A, V
GS
= 0V
40
V
I
D
= 250
μ
A, referenced to 25°C
36
mV
/
°C
V
DS
= 32V, V
GS
= 0V
V
GS
= ±20V, V
DS
= 0V
1
μ
A
μ
A
±10
On Characteristics
V
GS(th)
V
GS(th)
T
J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V
GS
= V
DS
, I
D
= 250
μ
A
1.0
1.8
3.0
V
I
D
= 250
μ
A, referenced to 25°C
-6.0
mV/°C
r
DS(on)
Static Drain to Source On Resistance
V
GS
= 10V, I
D
= 17.6A
V
GS
= 4.5V, I
D
= 14.9A
V
GS
= 10V, I
D
= 17.6A,
T
J
= 125°C
V
DS
= 5V, I
D
= 17.6A
6.3
7.3
7.0
9.0
m
9.9
11
g
FS
Forward Transconductance
84
S
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
R
g
Gate Resistance
V
DS
= 20V, V
GS
= 0V,
f = 1MHz
2665
325
200
2.2
3545
430
295
pF
pF
pF
f = 1MHz
Switching Characteristics
t
d(on)
Turn-On Delay Time
t
r
Rise Time
t
d(off)
Turn-Off Delay Time
t
f
Fall Time
Q
g
Total Gate Charge
Q
g
Total Gate Charge
Q
gs
Gate to Source Charge
Q
gd
Gate to Drain “Miller” Charge
V
DD
= 20V, I
D
= 17.6A,
V
GS
= 10V, R
GEN
= 6
11
6
37
5
47
25
7
9
20
13
60
11
66
35
ns
ns
ns
ns
nC
nC
nC
nC
V
GS
= 0V to 10V
V
GS
= 0V to 5V
V
DD
= 20V,
I
D
= 17.6A
Drain-Source Diode Characteristics
V
SD
Source to Drain Diode Forward Voltage
V
GS
= 0V, I
S
= 2.6A (Note 2)
V
GS
= 0V, I
S
= 17.6A (Note 2)
0.7
0.8
24
15
1.2
1.3
38
27
V
t
rr
Q
rr
Reverse Recovery Time
Reverse Recovery Charge
I
F
= 17.6A, di/dt = 100A/
μ
s
ns
nC
Notes
:
1:
R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R
θ
JC
is guaranteed by design while R
θ
JA
is determined by the user’s board design.
a. 40°C/W when mounted on a 1 in
2
pad of 2 oz copper
2:
Pulse Test: Pulse Width < 30
0
μ
s, Duty cycle < 2.0%.
3:
Starting
T
=
25
°
C
,
L
= 3mH
,
I
= 13A
,
V
= 40V
,
V
= 10V.
4:
The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
b. 62.5°C/W when mounted on a minimum pad.
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